JPH0311448A - Direct memory access control system - Google Patents

Direct memory access control system

Info

Publication number
JPH0311448A
JPH0311448A JP14533889A JP14533889A JPH0311448A JP H0311448 A JPH0311448 A JP H0311448A JP 14533889 A JP14533889 A JP 14533889A JP 14533889 A JP14533889 A JP 14533889A JP H0311448 A JPH0311448 A JP H0311448A
Authority
JP
Japan
Prior art keywords
transfer
data
dma
word
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14533889A
Other languages
Japanese (ja)
Inventor
Hideki Kamimaki
Nobuo Tsuchiya
Kiyokazu Nishioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Image Information Systems Inc
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Video Engineering Co Ltd filed Critical Hitachi Ltd
Priority to JP14533889A priority Critical patent/JPH0311448A/en
Publication of JPH0311448A publication Critical patent/JPH0311448A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To transfer word data similarly to byte data without complicating configuration by controlling the transfer bit width of data to be direct-memory- access (DMA)-transferred by a word transfer mode setting register.
CONSTITUTION: By the set value of the transfer bit width of transfer bit data by the word transfer mode setting register 2 and a DACK signal for DMA operation recognition from a DMA controller 1, an address switching control signal is outputted from a word transfer address switching control signal generating part 4, and an output address control signal is controlled. Thus, the DMA transfer data bit width is easily changed, and the word data can be DMA- transferred similarly to the byte data without complicating the circuit configuration.
COPYRIGHT: (C)1991,JPO&Japio
JP14533889A 1989-06-09 1989-06-09 Direct memory access control system Pending JPH0311448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14533889A JPH0311448A (en) 1989-06-09 1989-06-09 Direct memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14533889A JPH0311448A (en) 1989-06-09 1989-06-09 Direct memory access control system

Publications (1)

Publication Number Publication Date
JPH0311448A true JPH0311448A (en) 1991-01-18

Family

ID=15382866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14533889A Pending JPH0311448A (en) 1989-06-09 1989-06-09 Direct memory access control system

Country Status (1)

Country Link
JP (1) JPH0311448A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05252033A (en) * 1992-03-06 1993-09-28 Mitsubishi Electric Corp A/d converter
WO2001065384A1 (en) * 2000-03-03 2001-09-07 Sony Computer Entertainment Inc. Entertainment device
JP2005044343A (en) * 2003-06-21 2005-02-17 Samsung Electronics Co Ltd Portable storage device and method enabling free change in data bus width

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05252033A (en) * 1992-03-06 1993-09-28 Mitsubishi Electric Corp A/d converter
WO2001065384A1 (en) * 2000-03-03 2001-09-07 Sony Computer Entertainment Inc. Entertainment device
JP2005044343A (en) * 2003-06-21 2005-02-17 Samsung Electronics Co Ltd Portable storage device and method enabling free change in data bus width

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