JPH07334451A - Direct memory access controller system - Google Patents

Abstract

PURPOSE:To provide a DMA controller system capable of reducing transfer frequency between an I/O part and a memory and eliminating futile transfer time. CONSTITUTION:In the case of executing DMA transfer between the I/O part and the memory 5 having respectively different bus width, a CPU 4 releases a data bus, a timing control part 10 controls the timing of data reading from the I/O part in an I/O controller 6 and data storage from the controller 6 to a data latch part 9 and data read out from the I/O part by the control of the controller 6 are continuously stored in the data latch part 9 in each 8-bit unit through the data bus. Then, a timing control, part 10 controls the transfer timing of data from the latch part 9 to the memory 5 to transfer the data stored in the latch part 9 to the memory 5 through the data bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access controller device used in a personal computer or the like.

[0002]

2. Description of the Related Art In recent years, as the performance of microprocessors has increased, the data bus width of personal computers (hereinafter referred to as personal computers) has increased from 8 bits to 16 bits, 32 bits, and even 64 bits. There is. However, as a general-purpose interface (I / O) such as GPIB or SCSI, a conventional 8-bit wide interface is often used.

In the following, a direct memory access (hereinafter, DMA) when the bus width is different between the conventional I / O and the memory
The transfer will be described. FIG. 2 is a block diagram of a conventional DMA controller device that transfers data from I / O to memory. In FIG. 2, reference numeral 1 is an address generator that generates respective addresses for the I / O controller and the memory. Reference numeral 2 denotes a timing control unit that controls each timing of reading to the I / O controller and writing to the memory. Reference numeral 3 is a setting register for making settings relating to control of addresses and access timings.

The operation of the DMA controller device having the above components will be described below. First, the setting register 3 is set with the address of the data read register of the I / O controller, the start address and the end address of the data storage area of the memory.
When the I / O controller becomes readable, the DMA controller device reads the I / O controller. The DMA controller device starts the write operation to the head address of the memory when the data is determined in the middle of the read operation. When the write operation ends,
The read operation also ends, and one data transfer ends.

In this case, the data bus width of the memory is 32 bits, but the I / O address exists in 8-bit byte units and must be byte-accessible. In other words, 1 in DMA transfer between I / O and memory
Data transfer is performed byte by byte. When continuing the data transfer, the timing control unit 2 refers to the contents of the setting register 3 and rewrites the address registers 1c and 1d by incrementing the address counters 1a and 1b of the address generation unit 1 to write the memory address. The same operation is performed while incrementing.

[0006]

However, in the conventional DMA controller device as described above, when performing the DMA transfer between the I / Os having different bus widths and the memory, the I / O is transferred in 1 byte. Since one read time with respect to the O controller and one write time with respect to the memory are required as the transfer time, for example, when performing data transfer for 32 bits, an I / O having a bus width of 8 bits and Between the 32-bit memories, a transfer time of 4 times for the I / O controller and 4 times for the memory, that is, a total of 8 transfer times is required, resulting in a waste of the transfer time.

The present invention solves the above-mentioned conventional problems, and the transfer time can be shortened by reducing the number of transfers when performing DMA transfer between I / O and memories having different bus widths. It is an object of the present invention to provide a DMA controller device that can reduce waste of transfer time.

[0008]

In order to achieve the above object, a DMA controller device of the present invention is a DMA controller device for controlling DMA transfer between an I / O and a memory having different data bus widths. An output unit that controls the I / O and outputs the data read from the I / O to a data bus, and an address generator that generates the read address of the output unit and the memory address to which the data is transferred. Unit and a plurality of 8-bit registers, and a data latch unit for continuously storing the data output from the output unit to the data bus in the plurality of 8-bit registers, and the output unit from the I / O. Timing of reading data and storing it in the data latch unit and timing of transferring data stored in the data latch unit to the memory A timing controller for controlling, a configuration in which a bus control unit for controlling the opening and closing of the data bus.

[0009]

According to this structure, I having different data bus widths is used.
When performing a DMA transfer between the I / O and the memory, the bus control unit opens and releases the data bus, and the timing control unit reads the data from the I / O of the output unit.
Controls the timing of storing data from the output section to the data latch section. By this control, the data read by the control from the output unit for the I / O of the address generated by the address generation unit is continuously stored in the data latch unit in 8-bit units via the released data bus. To be done.

Thereafter, the timing control section controls the timing of transferring the data from the data latch section to the memory. By this control, the data stored in the data latch unit is transferred to the memory area of the address generated by the address generation unit via the released data bus.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A direct memory access controller device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a DMA transfer system using a direct memory access (hereinafter abbreviated as DMA) controller device of this embodiment. In FIG. 1, 4 is a CPU as a bus control unit having a 32-bit data bus, 5 is a memory having a 32-bit data bus, and 6 is an I / O as an output unit for controlling a GPIB interface (I / O). A controller (8-bit bus), 7 generates an address of the I / O controller 6, and an I / O address generation unit that constitutes an address generation unit,
Reference numeral 8 denotes a memory address generation unit which constitutes an address generation unit together with the I / O address generation unit 7 and generates an address of the memory 5, 9 denotes a data latch unit constituted by four 8-bit registers, and 10 denotes timing control. Part, 1
Reference numeral 1 is a control register unit for setting control data such as the timing control unit 10.

Here, the CPU 4, the I / O controller 6, the I / O address generation unit 7, the memory address generation unit 8, the data latch unit 9, the timing control unit 10, and the control register unit 11 are included. A DMA controller device is configured.

The operation of the DMA controller device of this embodiment will be described based on the operation of the DMA transfer system having the above components. External device to GPI
When data is input through a general-purpose interface (I / O) such as B, the I / O controller 6 causes the CPU 4
Is requested to release the bus by an interrupt. When the CPU 4 receives the bus release request, the CPU 4 releases the bus, notifies the DMA controller device that the bus has been released, and starts the DMA transfer.

The DMA controller device controls the I / O controller 6 from the I / O address generation section 7 to the I / O controller 6.
The address of the read register of the controller 6 is output, and at the same time, the read signal is output from the timing control unit 10. After the specified timing of the I / O controller 6 (100 ns in this embodiment), the timing control unit 10 outputs a latch signal to the first of the four 8-bit registers of the data latch unit 9. Data is continuously read from the I / O controller 6, and the data is stored in four registers of the data latch unit 9 via the system data bus which is a 32-bit bus.

When 32 bits of data are stored in the data latch unit 9, the memory address generation unit 8 outputs the start address of the memory area for storing the data to the memory 5, and at the same time, the data latch is latched on the data bus. The data is output from the unit 9, and the write signal of the memory 5 is output from the timing control unit 10 to the memory 5. After the specified timing of the memory 5 (100 ns in this embodiment), the write signal to the memory 5 ends, and the first data transfer of 32-bit data from the external device to the memory 5 ends.

After that, the memory address generator 8 repeats the above operation while incrementing the address of the memory area for storing data until there is no data input from the external device to the I / O controller. When the I / O controller 6 determines that the data input from the external device is completed, the I / O controller 6 interrupts the CPU 4 and ends the DMA transfer.

By the above operation, I / Os having different bus widths
The transfer time can be shortened by reducing the number of transfers in the case of performing the DMA transfer between the memory and the memory, and the waste of the transfer time in this case can be eliminated.

[0019]

As described above, according to the present invention, the bus controller opens and releases the data bus when performing the DMA transfer between the I / O and the memory having different data bus widths. The timing control unit controls the timing of reading data from the I / O of the output unit and storing the data from the output unit in the data latch unit. By this control, the data read by the control of the output unit for the I / O of the address generated by the address generation unit is continuously stored in 8-bit units in the data latch unit via the released data bus. can do.

After that, the timing control section controls the timing of transferring the data from the data latch section to the memory. By this control, the data stored in the data latch unit can be transferred to the memory area of the address generated by the address generation unit via the released data bus.

Therefore, the transfer time can be shortened by reducing the number of transfers when performing the DMA transfer between the I / O and the memory having different bus widths, and the waste of the transfer time in this case can be omitted.

[Brief description of drawings]

FIG. 1 is a block diagram of a DMA controller device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional DMA controller device.

[Explanation of symbols]

 4 CPU 6 I / O controller 7 I / O address generator 8 Memory address generator 9 Data latch 10 Timing controller

Claims (1)

[Claims] 1. A direct memory access controller device for controlling a direct memory access transfer between an I / O and a memory having different data bus widths, wherein the I / O is controlled and data read from the I / O is controlled. Output to the data bus, an address generation unit for generating the read address of the output unit and an address of the memory to which data is transferred, and a plurality of 8-bit registers. A data latch unit for successively storing the data output to the data bus in the plurality of 8-bit registers, and the output unit for the I / O
A timing control unit that controls the timing of reading data from the data latch unit and storing it in the data latch unit and the timing of transferring the data stored in the data latch unit to the memory; and a bus control unit that controls the opening and closing of the data bus. Direct memory access controller device equipped with.