JPS5938827A - Microprocessor ipl system - Google Patents

Abstract

PURPOSE:To change a program in a high speed, by providing an erasable and programmable read-only memory and an address counter and operating the address counter in an integer-fold speed of a main clock. CONSTITUTION:The program used by a microprocessor 19 is transferred from an internal random access memory 2 of a main storage device to an erasable and programmable read-only memory 7. Simultaneously, the control of the low-speed erasable and programmable read-only memory 7 is disconnected from a bus 9 connected to the high-speed microprocessor 19, and the speed conversion is made possible through an address counter 5, and the erasable and programmable read- only memory 7 is accessed in a low speed, and its contents are copied to the random access memory 2, thus changing the program.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a microprocessor IPL (initialization) method;
In particular, the present invention relates to a microprocessor IPL system using erasable and programmable read-on memory.

Conventionally, a program for a microprocessor has been written in a programmable read-only memory (FROM), so when changing this program, the contents of the programmable read-only memory must be changed. Therefore, the cost associated with changing the program is relatively high, and the microprocessor is stopped for a long time when the program is changed. Furthermore, if eraser pull-and-programmer pull-read-only memory (EPROM) is used as main memory program storage, the processing power, or throughput, of the microprocessor is reduced due to the slow speed of this type of memory. There were drawbacks.

An object of the present invention is to provide an erasable and programmable read-only memory and an address counter, and to eliminate the above drawbacks by operating the address counter at a speed that is an integral multiple of the main clock. The purpose of the present invention is to provide a processor IPL method.

The configuration for realizing the microprocessor IPL method according to the present invention includes a loader programmable read-only memory and a random access memory.

An address match timing control circuit, a counter control circuit, an address counter, an erasable and programmable read-only memory, a gated buffer,
It is equipped with nine microprocessors. The loader programmable read-only memory contains a program to be executed. The random access memory is for accommodating data sent from the erasable and programmable read-on memory via the data bus, and forms part of the main memory. The address match timing control circuit controls the address match timing of the address signal using a control signal. The counter control circuit is for sending a counter control signal from the address match timing control circuit to the address counter at a speed that is an integral multiple of the main clock in response to a write control signal or a read control signal.

The address counter operates under the control of a counter control circuit and is used to specify an address value. The erasable and programmable read-only memory is for sending out data used for initial setting according to the address value specified by the address counter.

The gate type buffer is used to control the sending of initial setting data using a counter control signal from the address match timing control circuit, and is provided with a temporary memory. The microprocessor is the main part that controls the operation of the entire system and executes sequences sequentially. In response to execution of a sequence by the microprocessor, initial setting data is sequentially loaded from the erasable and programmable read-only memory into a random access memory inside the main memory.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the microprocessor IPL system according to the present invention. In order to realize the microprocessor IPL method in FIG. , a gate type buffer 6, an eraseable and programmable read-on memory T, and a microprocessor 19. When the microprocessor 19Fi is reset or receives a non-maskable interrupt, it starts executing the program stored in the loader programmable read-only memory 1. A program contained in the loader programmable read-only memory 1 initially enables a write operation and opens the gate of the gated buffer 6.

The address match timing circuit 3 sends a counter control signal to the counter control circuit 4 via the counter control signal line 13ft. At this time, write control signal line 1
A counter reset signal is sent out via the counter 0, and this signal is sent out to the counter reset signal line 16 through the entire counter control circuit 4, and resets the address counter 5.

After the address counter 5 is reset, the first address of the erasable and programmable read-only memory 7 is accessed from the address counter 5 via the address signal line 17 of the erasable and programmable read-only memory. Therefore, the contents of the first address in the erasable and programmable read-only memory T are transferred to the gate type buffer 6 via the read data signal line 1B.
Sent to . This starts initialization of the main storage device.

Next, a program stored in the loader programmable read-only memory 1 sends out a continuous readout signal, and the gate of the gated buffer is opened to perform a readout operation. At this time, the address match timing control circuit 3 sends a gate control signal to the gate type buffer B via the gate control signal line 14. Gate type buffer 6
The gate of is connected to the gate control signal line 14 and the read control signal line 1.
1, the data from the υ read data signal line 18 is transferred to the data bus 9 via the gate 6.
Sent to . Immediately after initialization has started, the microprocessor 19 transfers data to the first address of the program area of the random access memory 2. Remember. The next time data is read from erasable and programmable read-only memory 7 via gated buffer 6, microprocessor 19 stores the data at a subsequent address in random access memory 2. On the other hand, immediately after the gated buffer 6 sends out data via the read data signal line 18, the address match timing control circuit 3 sends a counter control signal to the all counter control circuit 4 via the counter control signal line 13. At this time, the read control signal sent out through the continuous output control signal line 11t--, like a count-up pulse signal, increments the contents of the address counter 5 by 1 through the count-up pulse signal line 15. This is sent to the address signal line 17 as an address signal for the entire erasable and programmable read-only memory T, and the erasable and programmable read-only memory TV! -Access. In the erasable and programmable read-only memory T, the contents corresponding to the accessed address are read out and sent out via the read data signal line 18vc-. Then, in response to the read control signal sent out via the read control signal line 111, the microprocessor 19 stores the data in the corresponding address of the random access memory 2 via the gated buffer 6.

By repeating this read operation, the entire contents of the laser pull-and-programmable read-only memory 7 are copied to the random access memory 2, and the entire initial setting process is completed. Next, the loader programmable read-only memory 1 passes control to the program copied to the random access memory 2, and shifts the operation of the microprocessor 7 to the normal operating mode.

According to this embodiment, when changing a program, it is only necessary to remove the integrated circuit of the erasable and programmable read-only memory 7 from the socket and replace it with another one. For this purpose, it is sufficient to simply issue a non-maskable interrupt to the microprocessor 19. Furthermore, since this program is executed by the contents of the random access memory 2, it can be used as a low-speed erasable and programmable read-only memory 7 program memory.

As explained above, the present invention transfers the program used in one microprocessor from the random access memory inside the main storage device to the erasable and programmable read-only memory, and also controls the low-speed erasable and programmable read-only memory. Decoupled from the bus connected to the high-speed microprocessor, allowing speed conversion via an address counter to access the low-speed erasable and programmable read-only memory and copy its contents to random access memory;
This allows the program to be changed easily and inexpensively in a short time, and has the effect that the program can be executed at high speed even if a low-speed erasable and programmable read-only memory is used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a device for realizing a microprocessor IPL system according to the present invention. 1・Tatami・Loader Programmable read only memory 2・Repair・Random access memory 31 Scratch-address match timing control circuit 4...Counter control circuit 5...Address counter 6...Gate type buffer 7...Erasable and Programmable read-only memory 19...Microprocessor 8.9...Bus 10-18...Signal line Patent applicant NEC Corporation Representative Patent attorney Hisashi Inoro

Claims (1)

[Claims] A loader program read-only memory for storing a program to be executed, a random access memory forming part of the main memory for accommodating data from a data bus, and a control signal. an address match timing control circuit for controlling the address match timing of the host address signal; and a counter control signal from the address match timing control circuit in accordance with the write control signal or the Fi read control signal, and the counter control signal is controlled at a speed that is an integral multiple of the main clock. and a counter control circuit for sending out. an address counter for operating under the control of the counter control circuit; and an erasable and programmable read for sending initial setting data to the random access memory in accordance with an address value specified by the address counter. A microprocessor IPL method, characterized in that it is realized by comprising an only memory and a microprocessor for performing the initial execution based on a counter control signal from the address match timing control circuit.