KR19980033805A - Data Bus Selection Control Circuit of Semiconductor Memory Device - Google Patents

Abstract

The present invention discloses a data bus selection control circuit of a semiconductor memory device. The circuit is connected to a mode storage means for storing a request packet from an outside, on a predetermined number of data buses of the data bus, and turned on in response to a data bus selection control signal of data stored in the mode storage means. First switching means for transmitting the data transmitted to the second switching means, and second switching means for transmitting the ground voltage on the predetermined number of data buses in response to an inverted signal of the data bus selection control signal. have. Therefore, unlike conventional fixed 1 * 4, 1 * 8 products, or 1 * 9 products, it is possible to selectively operate with multiple products under the control of protocol commands according to the needs of the system.

Description

Data Bus Selection Control Circuit of Semiconductor Memory Device

The present invention relates to a semiconductor memory device, and more particularly, to a data bus selection control circuit of a semiconductor memory device.

The semiconductor memory device has an optional function that enables several functions in one chip as needed. As an example, it has an optional feature for bus data, with a layout that can accommodate both 1 * 4 and 1 * 8 physically within the chip. In addition, two methods are mainly used as an option processing method for the conventional 1 * 4 and 1 * 8. The first method is a selection process using a mask. In this method, a 1 * 4 mask and a 1 * 8 mask are separately fabricated using different patterns with one metal layer, and then a 1 * 4 device or a 1 * 8 device is commercialized by applying a mask according to the use. The second method is to use a fuse. A wafer is fabricated with a fuse that can distinguish 1 * 4 and 1 * 8 into a chip, and then a fuse cutting process is performed for 1 * 4 and 1 * 8. To make a 1 * 4 device or a 1 * 8 device. In addition to the optional processing of bus data, this option processing reduces costs by selectively processing various functions such as 2WE or 2CAS, power supply, 5V and 3.3V products.

However, the above-described conventional methods have a disadvantage in that an additional mask or a fuse in the chip and a fuse cutting process must be added to the wafer test process for optional processing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data bus selection control circuit of a semiconductor memory device capable of selectively controlling the data bus and eliminating the disadvantages of the prior art described above.

The data bus selection control circuit of the semiconductor memory device of the present invention for achieving the above object is a mode storage means for storing a request packet from the outside, connected to a predetermined number of data buses of the data bus and connected to the mode storage means. First switching means for transmitting data transmitted on the data bus by being turned on in response to a data bus selection control signal of the stored data, and turned on in response to an inverted signal of the data bus selection control signal to receive a ground voltage; And second switching means for transferring on a predetermined number of data buses.

1 is a circuit diagram of a data bus selection control circuit of a semiconductor memory device of one embodiment of the present invention.

2 is a circuit diagram of a data bus selection control circuit of a semiconductor memory device of another embodiment of the present invention.

Hereinafter, a data bus selection control circuit of a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

1 is a circuit diagram of a data bus selection control circuit of a semiconductor memory device according to one embodiment of the present invention, wherein a semiconductor memory device capable of inputting / outputting 9 bits of data is capable of inputting / outputting 8 bits of data. A data bus selection control circuit is shown for use as a device. Inverter 30 for inverting the control signal A and the CMOS transfer gate 10 in response to the control signal A on the data bus D9 for transmitting the most significant bit data while leaving the data buses D1-D8 intact. And a CMOS transfer gate 20 for transferring a ground voltage on the data bus D9 in response to the output signal of the inverter 30.

The operation of the above-described configuration is as follows.

In a high speed memory device, a protocol command is used. This command is given in a packet of 6 bytes in synchronization with an external clock signal. Among these packets, a packet including an operation code is called a request packet. In the present invention, the request packet is used. Rambus RAM should be initialized like any other dynamic memory device when used in a real system. At this time, a register write cycle for setting a mode is used in the chip. One or two bits of data to be written are allocated to enable 1 * 8 or 1 * 9 of bus data. That is, the request packet is stored in the mode register and generates a control signal A in accordance with the command stored in this register. If the control signal A is at a high level, the transfer gate 20 is turned on and the ground voltage is applied to the data bus D9 to operate 1 * 8. If the control signal A is at a low level, the transfer gate 10 is turned on to transfer data of the data bus D9 to 1 * 9. That is, the control signal A is generated according to the command stored in the mode register, and can operate as 1 * 9 or 1 * 8. The signal A is a signal generated by the mode register, and is a signal generated by bit data distinguishing 1 * 9 or 1 * 8 written to the mode register.

Fig. 2 is a circuit diagram of a data bus selection control circuit of another embodiment of the present invention so that the 1 * 8 device can also operate as a 1 * 4 device. Inverting the CMOS transfer gate 40 and the control signal B in response to the control signal B on each of the data buses D5-D8 that transfer the upper 4 bit data while leaving the data buses D1-D4 intact. And a CMOS transfer gate 50 for transferring a ground voltage on the data buses D5-D8 in response to an output signal of the inverter 60.

When the request packet is input in the same manner as described in Fig. 1, the packet is stored in the mode register and the data bus is selected in response to the control signal B generated by the bit data separating 1 * 4 or 1 * 8 of the instructions. This is done. If the control signal B is at a high level, the CMOS transfer gate 50 is turned on and the ground voltage is applied to the data buses D5-D8 to operate as a 1 * 4 device. On the contrary, when the control signal B is at the low level, the CMOS transfer gate 60 is turned on to transfer the data transferred to the data buses D5-D8 to operate as a 1 * 8 device.

In the above-described embodiment, the original 1 * 9 product can be operated as a 1 * 8 product, and the original 1 * 8 product can be operated as a 1 * 4 product, but the 1 * 9 product is 1 * by applying the method of the present invention. Not only 8 products but also 1 * 7 and below, 1 * 8 can be used as 1 * 4 as well as 1 * 7 -1 * 5, 1 * 3 or 1 * 1.

Therefore, unlike the conventional fixed 1 * 4, 1 * 8, or 1 * 9 products, the data bus selection control circuit of the semiconductor memory device of the present invention may selectively be controlled by the control of protocol commands according to the needs of the system. It can work as a product of.

Claims (3)

Mode storage means for storing a request packet from the outside; First switching means connected to a predetermined number of data buses of a data bus and for turning on in response to a data bus selection control signal of data stored in the mode storage means to transmit data transmitted on the data bus; And second switching means for turning on in response to an inverted signal of the data bus selection control signal to transfer a ground voltage on the predetermined number of data buses. . 2. The data bus selection control circuit of claim 1, wherein the first switching means is a CMOS transfer gate. 2. The data bus selection control circuit according to claim 1, wherein said second switching means is a CMOS transfer gate.