KR0142369B1 - Signal line control circuit for preventing system malfunction - Google Patents

Abstract

To the present invention a direct memory access cycle (Cycle DMA) or the cycle master (Master Cycle) or reproduction cycle (Refresh Cycle) a central processing unit (CPU) is floating (Floating) the address lines (Address Line) on the A ₂₄ --A ₃₁ A signal line control circuit for preventing a system malfunction, in which a voltage increase does not occur in a signal at an address of a signal, so that a central processing unit (CPU) in a computer system causes the address signal to be in a high impedance state. A circuit for adjusting a stable signal to a level when floating, comprising: a tree connected to a predetermined position between a hold acknowledge signal (HOLDA) line and an address line of a central processing unit (CPU); A logic circuit having an output in the form of a Tri-State;

A central processing unit (CPU) for controlling the operation of the peripheral device and performing arithmetic and logical operations; A system core chip for directly exchanging and controlling information during a direct memory access cycle (DMA cycle) or a master cycle or a refresh cycle; A video controller for controlling generation of a video signal sent to the video display device; It consists of a system memory and an address control logic to prevent malfunction of the system for a predetermined cycle to enable smooth and reliable computer operation.

Description

Signal line control circuit for preventing system malfunction

1 is a connection diagram of an address line and a central processing unit (CPU) of a conventional 486 computer.

2 is a circuit diagram of a first embodiment using 74F126 in accordance with the present invention.

3 is a configuration circuit diagram of a second embodiment using an inverter in accordance with the present invention using 74F125.

4 is a circuit diagram of a third embodiment for application only during a Master Cycle in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

10: Buffer 20: NOT Buffer

30: logical product (AND)

The present invention relates to a signal line control circuit for preventing a system malfunction, and more specifically, a central processing unit (CPU) address in a direct memory access cycle (DMA cycle) or a master cycle or a refresh cycle. The present invention relates to a signal line control circuit for preventing a system malfunction, in which a voltage line does not occur due to floating of an address line so that a signal enhancement does not occur in a signal of an address from A _{24 to} A ₃₁ .

The primary goal of a computer company is to manufacture a computer at a low cost while having high performance.

Therefore, for the high performance of the system, it is common to mount the input / output devices that were installed on the AT-Bus as a local bus (eg, a video controller, Integrated device electronics (IDE) controls, etc.)

In order to mount the I / O devices directly on the local bus, they must be connected directly to the address lines and data lines, which are local buses used by the central processing unit (CPU).

In this case, the local address line and the data line are equipped with local input / output devices in addition to the existing system core chip and memory, and also use the PAL for setting the address area for a special purpose. Programmable Array Logic).

1 is a circuit diagram of a central processing unit (CPU) and an address line in a conventional 486 computer system. In this system, a central processing unit (CPU) manages an address bus. In the case of a CPU cycle, there is no problem.

However, in the direct memory access cycle (DMA Cycle), bus master cycle, or refresh cycle (CPU), if the central processing unit (CPU) is a direct memory access cycle without governing the bungee bus, the direct memory In the case of a bus master cycle, a bus master card manages the access control, and in the case of a refresh cycle, a refresh controller manages the bus. The bungee bus is placed in the floating state (Tri-State).

In this case, A _0- A ₂₃ address used in the AT slot is special because it drives in the core chip or address control logic. No problem, but in the case of the 486 system, addresses above A _24- A ₃₁ are only used on the local bus and must be controlled in some way to stabilize the floating signal.

As shown in FIG. 1, in the related art, a pull down resistor is generally applied to an address line of A _{24 to} A ₃₁ to stabilize the address line in a low state.

However, for the special purpose of the system used during the central processing unit cycle, some of the signals in the address lines of A _24- A ₃₁ are used, e.g. to put video memory line addressing above the system memory address. In some cases, other devices may be connected to a separate device to perform bank switching using a PAL above a system memory address.

In such a system, if it is not a central processing unit cycle, the central processing unit floats the address line and the signal at address A _24- A ₃₁ is brought low by a pull down resistor. Although some of the addresses in A ₂₄ --A ₃₁ have a voltage drop on the pull-down resistor, the address lines appear to be high and the addresses that should be low are high. The system malfunctions.

The reason why the voltage drop that occurs at the same address lines. First, I _lC (Input to be any integrated circuit, which is the address lines are connected to address lines other than the central processing unit in order to be a low (Low) to a low (Low) Low Current flows out, but this current is fine but voltage drop occurs because it is combined in many sources such as several local devices.

When the voltage drop is more than 0.8V, it exceeds the TTL (Transisto-Transistor Logic) Low Voltage and may be recognized as high in some cases.

Secondly, integrated circuits (ICs) using high addresses from A _{24 to} A ₃₁ , for example, core chips or video chips, have defects in chip design or manufacturing. Due to process combinations, it is common to discharge excessive current (hundreds of uA) into the address line during operation without central processing unit cycles.

In this case too, a voltage drop may occur in the pull-down resistor, which may cause the system to malfunction.

Since the voltage drop is a current × resistance, it is conceivable that the voltage drop can be reduced by reducing the pull-down resistance value.

However, the resistance value cannot be reduced arbitrarily. Because the address line is directly connected to the central processing unit, when the central processing unit drives the address line high during the central processing unit cycle, if the pull-down resistance value is too small, the current flows too much The interior of the processing apparatus is burned out.

Therefore, the resistance value cannot be reduced because it cannot flow more than the maximum current allowed by the central processing unit specification.

Accordingly, an object of the present invention is to solve the above-described problems, and the central processing unit (CPU) in the direct memory access cycle (DMA Cycle) or master cycle (Refresh cycle) It is to provide a signal line control circuit to prevent the system malfunction by floating the Address Line so that no voltage drop occurs in the signal of the address of A _24- A ₃₁ .

In order to achieve the above object, the configuration of the present invention,

A signal line control circuit having a tri-state output connected to a predetermined position between a hold acknowledgment signal (HOLDA) line and an address line of a central processing unit (CPU). Logic circuits;

A central processing unit (CPU) for controlling the operation of the peripheral device and performing arithmetic and logical operations;

A system core chip for directly exchanging and controlling information during a direct memory access cycle (DMA Cycle) or a master cycle or a refresh cycle;

A video controller for controlling generation of a video signal sent to the video display device;

System memory and address control logic.

Hereinafter, the first, second, and third embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a first embodiment in which a logic circuit is constructed using model name 74F126 in accordance with the present invention, in which a central processing unit is configured to provide direct memory access, (DMA) and master ( Master) The operation of the cycle is explained as follows.

Direct Memory Access (DMA) Directly transfers data between a cycle memory and a peripheral device. The CPU does not operate by the central processing unit. The direct memory access control unit takes over the bus from the central processing unit.

In general, on AT compatible models, there are seven direct memory access channels (DMA Channels), four of which are 8 bits, and three of which are 16 bits, and each byte of each direct memory access cycle. ) Or data in word units.

This operation sequence is as follows.

1. The I / O controller activates the DRQ signal high when the direct memory access operation is required.

2) A system core chip detects a data request (DRQ) signal and sends a hold signal high to the central processing unit.

3) When the CPU receives a hold signal, the CPU processes the address bus, the data bus, and some of the control signals in a high impedance state to directly access a memory access controller (DMA controller). The System Core Chip makes these buses available, and then sends a Hold A signal to the system core chip.

In this way, the central processing unit floats all the address lines and passes the bus heading directly to the DMA controller.

4) The core chip receiving the hold A signal sends a data request confirmation signal to the I / O controller that requests the data request DRQ.

5) At this point, the direct memory access control, that is, the system core chip, is in charge, and the input / output controller generates an address to perform the direct memory access operation.

That is, data transfer is performed from the input / output peripheral to the memory or from the memory to the peripheral device.

In the master cycle (Maste Cycle) is similar to the direct memory access cycle, but not the direct memory access control, the Master Card (Master Card) is the bus master (Bus Master) in the mode (Mode).

There are two differences in how the master card carries out data requests (DRQs) on the AT bus when the master cycle is required, and in the same way as the direct memory access operation.

The first is to manage the bus by sending a master card or master # signal, and the second is to perform multiple data transfers, unlike direct memory access cycles.

Referring to FIG. 1, in the direct memory access cycle or the master cycle or the refresh cycle, the CPU floats the address line. A _24- A ₃₁ using a logic circuit of model name 74F126 to securely hold the address line in the low state during the cycle so that a voltage drop occurs in the signal at the address of A ₃₁ , thereby preventing the system from malfunctioning. A prevention signal line control circuit was constructed.

When the hold acknowledgment signal (HOLDA) enters the system core chip, i.e., the central processing unit (CPU) sends the hold acknowledgment signal (HOLDA) with the address floating and in a high impedance state. The hold confirmation signal HOLDA is input to the logic circuit in the form of a tree-state buffer of 74F126 through the buffer 10 to ensure that the address signals of A ₂₄ -A ₃₁ are reliably low.

The 74F126 buffer outputs the input state as it is when the control signal goes high, so the low, which is the input of the buffer, is reliably output during the hold confirmation period. Problems such as descent do not occur.

FIG. 3 is a block diagram showing the construction of a second embodiment in which a logic circuit is constructed with the model name 74F125 in the form of an inverter according to the present invention. A logic circuit having a tri-state output of model name 74F125 configured in the form of an inverter connected to a predetermined position between a HOLDA (HOLD Acknowledge signal) line and an address line;

A central processing unit (CPU) for controlling the operation of the peripheral device and performing arithmetic and logical operations; A system core chip for directly exchanging and controlling information during a direct memory access cycle (DMA cycle) or a master cycle or a refresh cycle; A video controller for controlling generation of a video signal sent to the video display device; A second embodiment composed of a system memory and an address control logic is shown.

Referring to Figures 2 and 3, the 74F125 consists of a 74F126 and an inverter respectively located between a hold confirmation signal (HOLDA) output line and an address line (A _24- A ₃₁ ) connected to the central processing unit and the system core chip. The logic circuits 10 and 20 perform the same operation as described above in their operation.

The fourth turn with each of the buffer coupled to the address in a first example the logic circuit 3 carried diagram to apply only during the master cycle (Master Cycle) According to the present invention, the address A ₂₄ In the context of the present invention to A ₃₁ A logic circuit connected in common to the input terminals of the buffers such that one input terminal is connected to the hold confirmation signal HOLDA line and the other input terminal is connected to the master # signal line; A central processing unit (CPU) for controlling the operation of the peripheral device and performing arithmetic and logical operations; A system core chip for directly exchanging and controlling information during a direct memory access cycle (DMA Cycle) or a master cycle or a refresh cycle; A video controller for controlling generation of a video signal sent to the video display device; A second embodiment composed of a system memory and an address control logic is shown.

In this way, the signals A _24- A ₃₁ are reliably low during the master cycle, and the master card performs the operation without malfunction.

Claims (6)

A circuit for adjusting a stable signal level when a central processing unit (CPU) floats an address signal in a high impedance state in a computer system, the holding confirmation signal (HOLDA) of the central processing unit (CPU). A logic circuit having an output in the form of a Tri-State buffer (model name 74F126) having a common input stage buffer 10 connected to a predetermined position between a HOLD Acknowledge signal line and an Address Line; A central processing unit (CPU) for controlling the operation of the peripheral device and performing arithmetic and logical operations; A system core chip for performing and controlling test information directly during a direct memory access cycle (DMA Cycle) or a master cycle or a refresh cycle; A video controller for controlling generation of a video signal sent to the video display device; A signal line control circuit for preventing a system malfunction, comprising a system memory and an address control logic. The signal line control circuit of claim 1, wherein the address line is selected and connected to a predetermined line. A circuit for adjusting a stable signal level when a central processing unit (CPU) floats an address signal in a high impedance state in a computer system, the holding confirmation signal (HOLDA) of the central processing unit (CPU) Has a tri-state buffer-type output consisting solely of an inverter buffer having a common input of a negative gate 20 connected to a predetermined position between a HOLD Acknowledge signal line and an address line. Logic circuits; A central processing unit (CPU) for controlling the operation of the peripheral device and performing arithmetic and logical operations; A system core chip for directly exchanging and controlling information during a direct memory access cycle (DMA Cycle) or a master cycle or a refresh cycle; A video controller for controlling generation of a video signal sent to the video display device; A signal line control circuit for preventing a system malfunction, comprising a system memory and an address control logic. The signal line control circuit of claim 3, wherein the address line is selected and connected to a predetermined line. In a computer system, a circuit that adjusts to a stable signal level when the central processing unit (CPU) floats an address signal to a high impedance state only during a master cycle, which is connected to an address. A logic circuit comprising an input terminal connected to each of the buffers and the input terminal of the buffers in common, the input terminal of which is connected to a hold confirmation signal (HOLDA) line, and the other input terminal is connected to a master # signal line; A central processing unit (CPU) for controlling the operation of the peripheral device and performing arithmetic and logical operations; A system core chip for directly exchanging and controlling information during a master cycle; A video controller for controlling generation of a video signal sent to the video display device; And a system memory and an address control logic. A signal line control circuit for preventing a system malfunction. The signal line control circuit of claim 5, wherein the address line is selected and connected to a predetermined line.