JPH0362248A - Memory controller - Google Patents

Abstract

PURPOSE:To easily attain the DMA transfer to the 32-bit and 16-bit external memories by providing a transceiver between a DMA controller and the external memories to control higher and lower 16 bits out of 32 bits as well as 32 bits. CONSTITUTION:The external memories 2A and 2B have the data widths of 32 buts and 16 bits respectively. The transceivers 3A - 3C transfer data between a DMA device and both memories 2A and 2B by an enable signal. The transceivers 3A, 3B and 3C perform the control the data of 32 bits, the data of lower 16 bits, and the data of higher 16 bits respectively. Thus the DMA transfer is attained between an external memory 2 of 32 bits or 16 bits and a DMA device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a memory control device using DMA transfer control for high-speed data transfer.

(Prior art) DMA (D
Direct Memory Access) is known.

In a memory system equipped with a DMA controller, D
A single external memory having the same data bit width as that of the MA controller is often used. In such a memory system, the amount of data (number of bits) that can be handled in one memory access during DMA transfer by the DMA control device depends on the bit width of the data bus of the DMA control device and the external memory. For example, if a D ki A control device with a data bit width of 32 bits is used, the external memory will necessarily also have a data bit width of 32 bits, and the amount of data handled in one access will be limited to 32 bits.

(Problems to be Solved by the Invention) According to the conventional method, the data bit width of the external memory is determined by the data bit width of the DMA control device, and when performing DMA transfer with a different data bit width,
There were problems such as restrictions on the configuration of peripheral circuits including external memory.

This invention was made in view of the above circumstances, and for example, 32 bits in 32 bit DMA.

An object of the present invention is to provide a memory control device that can perform DMA transfer to both 16-bit external memories.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an external memory configured with an n-bit data width and a 20-bit data width, and a DMA control device with a 20-bit transfer capability, which is different from the CPU. In the information processing device connected via the DMA control device, an address decoder generates a signal for selecting an external memory by decoding the upper address among the addresses continuously generated from the DMA control device; A transceiver that is controlled by the lower bits and transfers data between the DMA control device and an external memory configured with a data width of 2n bits, and an external memory configured with a data width of n bits, , a transceiver that transfers each lower order, and an address counter within the DMA control device that switches and sequentially updates an address for n-bit data and an address for 2n-bit data.

(Function) As described above, the present invention applies the lower address (A1: word address) of the DMA control device to external memories of 32-bit and 16-bit configurations.

A2: Controlled by longword address), 32
A 32-bit transceiver that transfers data to bit memory, a transceiver that transfers the upper 16 bits of 32-bit data to 16-bit memory, a transceiver that transfers the lower 16 bits, and word address calculation inside the DMA. It consists of an address counter that can sequentially count up addresses by switching between longword address calculation and. A transceiver for controlling 32 bits and 16 bits each of the upper and lower 32 bits is provided between the DMA control device and the external memory,
By controlling them with address values, 3
DMA transfer to 2-bit memory becomes possible. This allows for flexible system construction.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 denotes a DMA control device, which independently controls DMA transfer without being controlled by a CPU (not shown). Reference numeral 2 denotes an external memory, which is divided into 2A and 2'B depending on its bit structure. 2A has a bus width of 32 bits, and 2B has a bus width of 16 bits.

Code 3 is a transceiver, and 3A is 32 bits.

3B controls the lower 16 bits of data, and 3G controls the upper 16 bits of data. The code 4 is an address counter, 4A is a long word (32 bits) address, and 4B is an address counter.
controls word (16 bit) addresses. Reference numeral 5 denotes an address decoder, which generates a signal (chip select, C8) for selecting the external memories 2A and 2B by decoding the upper address. Reference numeral 6 denotes a gate circuit, which determines whether the upper word or lower word of the 16-bit memory is based on the address A, and outputs a signal to control the transceivers 3B and 3C accordingly.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. D
The MA control device 1 is a unit that is located between the external memory 2 and a main memory (not shown) and controls DMA transfer. External memories 2A to 2B have data widths of 32 bits and 16 bits, respectively. Transceivers 3A to 3C exchange data between the DMA and external memories 2A to 2B using enable signals. Transceiver 3A controls 32-bit data, 3B controls lower 16 bits, and 3C controls upper 16 bits. 4A to 4B are address counters,
The address counter 4A controls the long word address, and the address decoder 5 outputs the chip select signal (32CS).
) or generate the 16C5 signal, transceiver 3A
~32-bit external memory 2A by controlling 3C
Controls DMA transfer between 16-bit external memories 2B and 16-bit external memory 2B. The address counter 4B controls the word address, and uses the gate circuits 6A to 6B to control the 16-bit transceivers 3A to 3C and the external memory 2B.

When sequential address access is performed, 32-bit or 16-bit external memory 2 and D
Data transfer between the MA devices 1 is performed by the transceiver 3 using a long word address generated by the address counter 4, a word address, and a signal obtained by decoding the upper address according to the address map of each external memory 2A to 2B.
control. This allows 32-bit or 16-bit
DMA transfer is performed between the bit external memory 2 and the DMA device 1.

[Effects of the Invention] As explained above, the present invention provides a transceiver that controls 32 bits and 16 bits each of the upper and lower 32 bits between the DMA control device and the external memory, and controls them using address values. By controlling it, DMA transfer with 32-bit or 16-bit external memory is easily possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1... DMA control device, 2... external memory, 3...
・Transceiver, 4...Address counter, 4...
gate circuit.

Claims (1)

[Claims] In an information processing device in which external memories each having an n-bit data width and a 2n-bit data width are connected to a CPU via a DMA control device with a 2n-bit transfer capacity, data is continuously generated from a DMA control device. is controlled by an address decoder that generates a signal for selecting an external memory by decoding the upper address among the addresses to be sent, and the lower bit of the address,
A transceiver that transfers data between a DMA control device and an external memory configured with a 2n-bit data width, and a transceiver that transfers the upper and lower 2n-bit data, respectively, to the external memory configured with an n-bit data width. and an address counter within the DMA control device that switches and sequentially updates an address for n-bit data and an address for 2n-bit data.