JP2612715B2 - Address bus controller - Google Patents

Description

The present invention relates to controlling a bus of a data processing system,
In particular, the present invention relates to an address bus control device for dynamically controlling connection switching between a plurality of buses having different address data widths and a device having a smaller address data width.

[Conventional technology]

In a data processing system mainly composed of a microprocessor, a bus configuration having a bus connecting a microprocessor and a memory, a bus connecting an I / O group, and a buffer gate interposed between these buses is often used. Adopted. In recent years, as microprocessors have become more sophisticated, the address space that can be handled, that is, the width of address data (the number of bits) has been expanded. I have. However, such an address space is too large for an I / O group. Therefore, it is common practice to set the address data width of the system bus to be smaller (for example, 28 bits, 256 MB), thereby reducing the hardware of the address signal lines and the decoder.

By the way, some I / O groups to be connected to the system bus have been developed in accordance with various conventional microprocessors having various address spaces, and some of the I / O groups have a system bus designed as described above. A device having an address data width smaller than the address data width is also included.
Such a device cannot perform data transfer by DMA through this system bus. Therefore, it has been conventionally performed to provide a bank setting register for compensating for the shortage of address bits, thereby enabling DMA via this system bus.

It should be noted that the microcomputer system includes an internal bus dedicated to the central processing unit and an external bus also used by other devices, use of specific bits of address data as bus identification information, and supplementation of insufficient address bits by a bank setting register. One example is described in JP-A-60-235268.

[Problems to be solved by the invention]

With such a bus control mechanism, it is impossible to dynamically select and switch between the memory bus and the system bus for a device having a smaller address data width than the system bus, and to perform DMA via any of them. It is.

An object of the present invention is to eliminate the above-mentioned restriction, that is, a device connected to a system bus and having a smaller address data width dynamically switches a system bus and a memory bus having a different address data width from the system bus.
An object of the present invention is to provide an address bus control device which can perform DMA through any of them.

[Means for solving the problem]

An address bus control device according to the present invention includes a first bus (for example, a memory bus) and a second bus (for example, a system bus).
Means for receiving a predetermined portion of address data as bus identification information from a device connected to the second bus having a smaller address data width than any one of the above, and address data widths of the first bus and the second bus. First and second data holding means for holding data satisfying a difference in data width from address data from the device excluding the bus identification information, and wherein the bus identification information corresponds to the first bus in response to the bus identification information. , The address data from the device except the bus identification information is transferred from the second bus to the corresponding portion of the first bus, and the contents of the first data holding means are transferred to the corresponding portion of the first bus; If the bus identification information indicates the second bus, there is provided transfer means for transferring the contents of the second data holding means to a corresponding portion of the second bus. It is preferable that data is set from these processors to these data holding means.

[Action]

If the bus identification information indicates that access to the first bus is requested, the address data excluding the bus identification information from the device and the contents of the first data holding means are linked, and Address data having a predetermined data width is formed and sent to the first bus. Also,
If the bus identification information indicates that access to the second bus is requested, the contents of the second data holding means are combined with the address data excluding the bus identification information from the device on the second bus. Thus, address data having a required data width is formed. Therefore, the switching between the DMA via the first bus and the DMA via the second bus can be performed dynamically.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a data processing system including an embodiment of the present invention. In FIG. 1, 1 is a CPU using a 32-bit address, 2 is a memory, 3 is a path control circuit, and 4 is a 32-bit address. 5 is a system bus for a 28-bit address, 6 is an address bus of the lower 23 bits of the system bus 5, 7 is an address bus of the remaining upper 5 bits, 8 is an address specifying a path, 9 Is 28
A slave device uses a bit address, and 10 is a master device using a 24-bit address.

FIG. 2 is a diagram showing the details of the path control circuit 3;
6, 7, and 8 indicate the same reference numerals in FIG. 1, 11 is an enable signal, 12 is a data bus of CPU 1, and 13 and 14 are ANDs.
Gate, 15 is NOT gate, 16 and 17 are data bus 1 of CPU1
A 9-bit and 5-bit flip-flop group, each of which can be set to an arbitrary value via 2, 18, 19 and 20 are driver gates.

FIG. 3 shows that the master device 10
FIG. 21 is a diagram showing an address flow at the time of carrying out the operation. Reference numeral 21 denotes a 24-bit address signal M0 to M23 output from the master device 10, and 22 denotes 9-bit data MF0 to MF8 in the flip-flop group 16.
23 is a 32-bit address signal MA0-MA3 on the memory bus 4
Is one. FIG. 4 is a diagram showing an address flow when the master device 10 performs DMA via the system bus 5, where 21 is an address signal output from the master device 10 as in FIG. 3, and 24 is a flip-flop. The 5-bit data SF0 to SF4 and 25 in the group 17 are 28-bit address signals SA0 to SA27 on the system bus 5.

In FIG. 1, a master device 10 using a 24-bit address sends the lower 23 bits of the address to an address bus 6 and sends the most significant bit as a path designation address 8 to a path control circuit 3.

Next, the master device 10 transmits the DMA
2 and FIG. 3 will be described with reference to FIG. 2 and FIG. Most significant bit M2 output by master device 10
When 3 (pass designating address 8) is "0", the enable signal 11 enables the driver gate 18 via the AND gate 13, and the flip-flop group 16 arbitrarily set in advance via the data bus 12 of the CPU 1 Bit data MF0 to MF8
Is output to the upper 9 bits of the memory bus 4. The enable signal 11 passed through the AND gate 13 enables the driver gate 20 and the 23 bits on the address bus 6
M0 to M22 are output to the lower 23 bits of the memory bus 4. As described above, the master device 10 using the 24-bit address is connected to the memory bus 4 for the 32-bit address.
Addressing can be performed via (MA0 to MA31), and data transfer with the memory 2 can be performed.

On the other hand, the processing of the address signal when the master device 10 performs the DMA via the system bus 5 will be described with reference to FIGS.
Referring to the figure, the most significant bit M2 output by the master device 10 is shown.
When 3 (path designating address 8) is “1”, the enable signal 11 enables the driver gate 19 via the AND gate 14 which receives this signal via the NOT gate 15, and is previously set via the data bus 12 of the CPU 1. The 5-bit data SF0 to SF4 of the flip-flop group 17 arbitrarily set is transferred to the system bus 5
To the address bus 7 of the upper 5 bits. This allows the master device 10 using a 24-bit address to
System bus 5 for bit addresses (SA0 to SA2)
Addressing can be performed via 7), and data transfer with the slave device 9 can be performed.

〔The invention's effect〕

According to the present invention, in a data processing system having two buses connected via a buffer gate, a device using address data having a smaller data width than these buses is directly connected to one of the buses, and DMA by the device is used.
Can be performed while switching the bus to be used to dynamic. This feature makes it easy to configure a system by combining a new processor with an extended address space with a conventional I / O group having a smaller address space.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data processing system having an embodiment of an address bus control device according to the present invention. FIG. 2 is a block diagram showing details of a path control circuit in FIG. 1 which is an embodiment of the present invention. FIG. 3 and FIG. 4 are diagrams schematically showing the processing of address data by the circuit of FIG. 1 ... CPU, 2 ... Memory, 3 ... Path control circuit as an example of an address bus control device, 4 ... Memory bus having an address data bus having a width of 32 bits, 5 ... Address data bus having a width of 28 bits , The lower 23 bits of the address bus of the system bus, the upper 5 bits of the address bus of the system bus, the master device using the address data having the width of 10 to 24 bits, the bus identification Address bits, 13 to 15, 18 to 20... A transfer circuit responding to the bus identification bit, 16... A first data holding circuit, 17.
... Second data holding circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page (56) References JP-A-58-225422 (JP, A) JP-A-59-206925 (JP, A) JP-A-61-74040 (JP, A) JP-A-61-74040 74046 (JP, A)

Claims (2)

(57) [Claims] A first bus connecting a processor and a memory; and a second bus connecting an I / O group, wherein the I / O group has an address data width of any one of the first bus and the second bus. A data processing system including a device using address data having a smaller data width, a means connected to the device and receiving a predetermined portion of address data from the device as bus identification information; First and second data holding means for holding data satisfying a difference between each address data width of the second bus and a data width of address data from the device excluding the bus identification information; and If the bus identification information indicates the first bus in response to the bus identification information, address data from the device except the bus identification information is transmitted from the second bus to the second bus. The contents of the first data holding means as well as transferred to the corresponding portion of the serial first bus first
An address bus control device comprising: transfer means for transferring the contents of the second data holding means to the corresponding part of the second bus if the bus identification information indicates the second bus. 2. The address bus control device according to claim 1, wherein the data held in said first and second data holding means is supplied from said processor.