JPS6022777B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an improved data processing system in which a main memory and memory-using devices such as a central processing unit and an input/output control unit that access the main memory are connected by a common data bus. Regarding data transfer method.

Generally, in an integrated data processing system, a central processing unit (hereinafter referred to as CPU) and one or more input/output control units (hereinafter referred to as IO) are connected to the data bus line.
C) are connected.

Input/output devices are connected to the IOC.In particular, the IOC to which high-speed input/output devices are connected has a function (DMA:D
Some have ireotMemory Access). Input/output control in a data processing system refers to data transfer control between a CPU or main memory and an input/output device. The data transfer control includes a method of transferring data between the input/output device and the main memory IJ while executing input commands under program control, and a method of transferring data between the input/output device and the main memory IJ independently of program control. There is a DMA method that directly transfers data. In the former method, the program runs each time one word is transferred, so the data transfer speed is slower than in the DMA method. Therefore, the system using input/output instructions is used for low-speed input/output devices, while the DMA system is used for high-speed input/output control devices. The above DMA
In this method, the IOC has hardware control functions necessary for independent data transfer between the main memory and the main memory, and the control functions are controlled by the commands given from the CPU.
Data transfer is performed in the form of ``clesteal''.

When this DMA method is used, the IOC and CPU may have to wait when accessing the main memory, but at other times they can operate in parallel, allowing high-speed data transfer. By the way, one effective method for speeding up transfer using the DMA method is to
The goal is to increase the amount of data exchanged with the OC or CPU.

That is, the width of the data transfer bus must be widened. However, IOCs (including input/output devices) that were connected to conventional narrow data transfer width buses cannot be connected to electronic computers having newly designed wide data transfer buses. Therefore, in order to improve the processing speed of a computer system, there is a drawback that all IOCs (including input/output devices) must be new IOCs that can be connected to a new data transfer bus. The present invention eliminates the above-mentioned drawbacks. For example, the data width of one input/output is 32 bits.
In data transfer between MA device and main memory, 32-bit data transfer is performed.For example, in data transfer between DMA device and main memory, data width of 16 bits is input/output at one time, 16-bit data transfer is performed. The purpose of the present invention is to provide a data transfer method that enables the following. Another object of the present invention is to perform 16-bit and 32-bit data transfer using one data transfer bus, and to control the data transfer using a zone designation signal.

Another object of the present invention is to enable detailed memory writing in byte units using the zone designation signal in newly expanded data transfer in 32-bit units.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of the present invention. As is clear from the figure, the system to which the present invention is applied includes a main memory MMUIO, a memory control unit MCUI I, a central processing unit 12, and 32-bit direct memory access channels DMAC#1 and #2.
13, 14, and 16-bit direct memory access channel DMAC#15, a 16-bit/32-bit data bus 16, a zone designation line 18, and a memory address/control line 19.
The above-mentioned direct memory access channel is a DMA device including an input/output control device IOC and an input/output device, and is hereinafter referred to as DMAC. And DMAC13,1
4 is a channel for transferring expanded 32-bit data, and DMAC15 is a channel for transferring 16-bit data, which has been in the past. In the present invention, 16-bit or 32-bit data transfer via the data bus 16 is controlled by a zone designation signal.

The zone designation signal is sent to the CPU 12 and the DMAC 13,
14 and energizes the zone designation line 18.
Therefore, zone designation line 18 and CPU12 and DM
The ACs 13 and 14 can be wired or connected.
A memory control unit 11 (hereinafter referred to as FMCU) to which the zone designation line 18 is connected
main memory 10 based on the contents of activated line 18
The memory peripheral circuit is controlled to perform data transfer between the CPU 12 and the DMAC 13 and 14 using the full bit width (ie, 32 bits) of the data bus 16. Further, the memory control unit 11 generates a write enable signal based on the contents of the activated zone designation line 18 so that a free write operation can be performed in units of bytes. That is, CPU12 and DMAC13
, 14 to the main memory 10, 32-bit data can be freely written in byte units.
Therefore, by the zone designation signal, the zone designation line 18
When energized, memory control unit 1 1 becomes 3
At the same time as performing data transfer control in 2-bit mode, write control is performed in units of bytes in write operations.
Note that the write operation in units of bytes described above will be understood in FIGS. 2 and 3, which will be described later. on the other hand,
The OMAC 15, which performs 16-bit data transfer with the main memory 10, is not connected to the zone designation line 18 described above.

Therefore, when data is transferred between the DMAC 15 and the main memory 10, the MCUII performs control in a 16-bit data transfer mode. At this time, the transfer data is transferred using, for example, the lower 16 bits (bits 0 to 15) of the 32-bit data bus 16. Further, in a write operation from the DMAC 15 to the main memory 10, the write operation can be freely performed at either an odd numbered address or an even numbered address in the main memory 10. FIG. 2 is a block diagram showing the configuration of the main memory 10 used in the present invention and its peripheral circuits.

Further, FIG. 3 shows a circuit that generates a control signal and a zone designation signal for controlling the gate circuit of FIG. 2. The circuit shown in FIG. 3 is provided within the MCUII. The operation of writing transferred data into the main memory 1 and extracting the transferred data will be described below with reference to FIGS. 2 and 3. The main memory 10 shown in FIG. 2 is composed of 32 bits per word, and four zones (zone 0 to zone 3) are specified in units of 8-bit bytes. Further, the king-edge memory 10 has two addresses for one word in units of 16 bits, and has an even number address and an odd number address for one word. The write data transferred from the data bus 16 is input to the main memory 10 via gate circuits 21, 22, and 23. The data read from main memory 10 is then output to data bus 16 via gate circuits 24, 25, and 26. Therefore, data bus 16
consists of a bidirectional bus. Note that although the address circuit and the like are omitted in this figure, it should be understood that the address circuit is provided using a well-known technique. Control signals generated from the circuit shown in FIG. 3 are inputted to the gate circuits 21 to 26. below,
Using both FIG. 2 and FIG. 3, data transfer according to the present invention will be explained with a focus on main memory write and issue operations.

Since the circuit configuration shown in FIG. 3 is easily understood, the operation will be explained below. CPU1 2 and D
An example of a write operation from the MACs 1 3 and 1 4 to the main memory 10 will be described below using the DMAC 13 as an example.

As already detailed in FIG. 1, 32-bit data from the DMAC 13 is transferred to the main memory 10 via the data bus 16.

At the same time, the zone designation line 18 is activated from the DMAC 13, and memory address/control signals are transferred to the MCUI I via the line 19. It should be noted that if the memory configuration is 32 bits per word used in the embodiment of the present invention, it can be understood that the zone designation line 18 is composed of four lines. This is because the signal from the zone designation line 18 can directly serve as a signal for obtaining a byte-by-byte write enable signal to the main memory. Now, when one to four of the zone designation lines 18 are energized to a low level as described above, a high level output Z is sent from the NOR gate 31 to the output line via the wired OR 30 shown in FIG. Obtained from 32. Further, a rotary bell output is also obtained from the output line 34 of the OR gate 33 having a logic output of Z1Z/MA. The output line 32 and the output line 34 are connected to the gate circuits 21 and 22 shown in FIG.
・The high level output of MA and Z is provided by the gate circuit 21,
22 is energized to a low level via an inverter on the input side. Therefore, the 32-bit data transferred from the DMAC 13 is transferred from the data bus 16 to the gate circuit 21,
22 and is transferred to the main memory 10. By the way, it has already been explained that the 32-bit write data transferred through the data bus 32 can be freely written in byte units to the main memory 10 according to the activation content of the zone designation line 18. That is, as can be understood from FIG. 3, the high level output of the output line 32 is directly output to
It is input to one of the D gates 35 to 38, and the A
The other input of the ND gates 35 to 38 is an inverter 39.
This is the energizing signal of the zone designation line 18 inputted via the lines 1 to 42. Therefore, zone designation line 1 8 (
When ZONOO) to (ZON04) are activated, the corresponding AND gates 35 to 38 operate, and a high level output is obtained. and. The AND gates 35 to 3
The output of 8 passes through OR gates 43 to 46 and is further
It is input to the other of ND gates 47 to 50. The NAND gate 47 is synchronized with the write timing signal.
Low level write enable outputs WEO-WE3 are available from output lines 51-54. These output lines 51 to 54 are connected to the main memory 1 shown in FIG.
The inverter on the input side energizes zones 0 to 3 at a high level. Therefore, except for the 32-bit data inputted through the gate circuits 21 and 22, the write enable signal W
Data can be freely written in byte units to designated addresses in the main memory 10 using EO to WE3. For example, when writing only to zone 0, by energizing the zone designation line ZONOO, the inverter 39, AN
A write enable signal WEO is obtained through the D gate 35, the OR gate 49, and the NAND gate 46.
The transferred data (0 bits to 7 bits) is written to zone 0 of the designated address of the main memory 10 by EO. It is understood that according to the present invention, there are 15 write operations. Also, in the read operation from the main memory 10, the zone designation signal from the DMAC 13 causes the output Z from the circuit in the MCUII shown in FIG.
and outputs Z+Z·MA are obtained from output lines 32, 34, which energize gate circuits 24, 26 of FIG.

Then, the contents of the memory address specified by the DMAC 13 are read from the main memory 10, and the contents of the memory address specified by the DMAC 13 are read out from the main memory 10.
The 2-bit data is output to the data bus 16 via the gate circuits 24 and 26, and further transferred to the DMAC 13. Note that the data transfer described above is performed using the CPUIO
The same applies to the DMA device of the DMAC14.

On the other hand, data transfer between the 16-bit DMAC 15 and the main memory 10 can be performed in a similar manner by considering the 32-bit DMAC 14 as 16 bits as one zone. That is, data from DMAC 15 is transferred to main memory 10 using the lower 16 bits of data bus 16, while memory address and control signals are input via line 19 to MCU II.
The MCUII controls writing of the transferred 16-bit data to an odd numbered address or an even numbered address in the main memory 10 based on the least significant bit MA of the memory address. That is, in the case of 16-bit data transfer in the circuit shown in FIG. 3, since the zone designation line is not activated, the output of the NOR gate 31, which has been input at a high level, becomes a low level. Then, a high level output is obtained from the inverter 60. At this time, the least significant bit MA of the memory address
When is "0" (that is, an even address is specified), a high level output is obtained from the input line 61, and the AND gate 62 operates. Then, the output of the AND gate 62 is passed through the OR gate 33, and a high level output is obtained from the output line 34 having a logic output of Z+Z.MA. This world power Z1Z・MA is the gate circuit 2 in Figure 2 as above.
The gate circuit 21 is energized to a low level via the inverter on the input side of 1. Therefore, the write data transferred using the lower 16 bits of the data bus 16 is transferred to the main memory through the gate circuit 21. At this time, in the circuit shown in FIG. 3 as well, the AND gates 64 and 65 to which the lowest bit MA signal of the address from the input line 61 and the output of the inverter 60 are input operate, and the signal is passed through the OR gates 43 and 44. Furthermore, NAND gate 47,4
At 8, low level write enable signals WE0 and WEI are obtained from output lines 51 and 52, synchronized with the write timing signal. The write enable signals WE0 and WE2 are also applied to the main memory 1 in FIG.
It is applied to zone 0 and zone 1 of 0. Therefore, 1
6-bit write data is written to a designated even address in main memory 10. In addition, when the DMAC 15 performs a reading operation from an even numbered address in the main memory 10, an output signal Z0Z·MA is obtained from the output line 34 from the circuit shown in FIG. 3 based on the memory address indicating an even numbered address.

Then, the gate circuit 24 shown in FIG. 2 is energized by the signal. Therefore, the lower 16 bits of the specified even address (
The contents of bits 0 to 15 are outputted to the data bus 16 via the gate circuit 24 and transferred to the DMAC 15. On the other hand, when the least significant bit MA of the memory address from the DMAC 15 is "1" (that is, an odd address is specified), the input line 61 is energized, so the output of the inverter 60 and , least significant bit M
The AND gate 66, in which the A input is inputted with the high level output of the inverter 7, operates, and the output Z of the rotten bell is activated.
- MA is obtained by output line 67;

The output line 67 is connected to the gate circuit 23 of FIG.
The inverter on the input side energizes it to a low level. Therefore, if the write address from the DMAC 15 indicates an odd address, the lower 1 of the data bus 16
The write data transferred using 6 bits is about to be input to the zone 2 and zone 3 sides of the main memory 10 through the gate circuit 23. At this time, AND gates 68 and 6 to which the output of the inverter 63 in FIG.
9 operates, and through the or gates 45 and 46, NA
The ND gates 49 and 501 are synchronized with the write timing signal to output a low level write enable signal W.
E2 and WE3 are obtained from output lines 53 and 54. The write enable signals WE2 and WE3 are applied to zones 2 and 3 of the main memory 10 in FIG. Therefore, 16-bit write data passes through the gate circuit 23 and is written to the designated odd address of the main memory 10.
Further, when the DMAC 15 performs a read operation from an odd address in the main memory 10, an output signal Z·MA is obtained from the output line 67 from the circuit shown in FIG. 3 based on the memory address indicating the odd address.

Then, the gate circuit 25 shown in FIG. 2 is energized by the signal. Therefore, the upper 16 bits (1
6 bits to 31 bits) are transferred to the lower 16 bits of the data bus 16 via the gate circuit 25, and
Data is transferred to the MAC 15. As is clear from the above explanation, the data transfer method of the present invention can improve the processing speed of existing computer systems, for example by
Only devices with a high data transfer rate such as , memory, and disks can be replaced with new devices, and all other input/output devices can be used as existing devices. Therefore, system performance can be improved at low cost.In other words, a device that is allowed to occupy the data bus can change the data transfer mode of the data bus to 1 depending on the activation content of the zone designation line every bus occupancy period.
It can be set to either 6-bit mode or 32-bit mode. Therefore, it is possible to design a system that uses both DMA devices that use 16-bit mode and DMA devices that use 32-bit mode. Can be connected to the bus. Additionally, DMN devices that use the newly designed 32-bit mode can utilize 32-bit wide data transfer capability and byte-by-byte write control functions.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the system configuration of the present invention, Figure 2 is a block diagram showing the system configuration of the present invention.
This figure shows the configuration of the main memory used in the present invention and its peripheral circuits, and FIG. 3 is a diagram showing a circuit within the memory control unit that generates control signals for controlling the peripheral circuits of FIG. 2. 10...Main memory, 11...Memory control unit, 12...Central processing unit, 13,14. ．． ．．
．． ．． ．． 32-bit direct memory access channel, 15...16-bit direct memory access channel, 16...data bus, 18...zone designation signal line, 19...memory address control signal line. Traditional Figure 2 Traditional Figure 3

Claims (1)

[Claims] 1 One word is divided into multiple zones, and a main memory is allocated to each zone so that it can be accessed, and a common memory address bus/control line and one-word length data bus are connected to this main memory. In an information processing system having a plurality of direct memory access control devices connected to a data bus and controlling data transfer of one word length or a data width of a part of one word length, a first direct memory access control device that controls input/output of the data bus; a second direct memory access control device that controls only data transfer of a partial data width via the data bus; and a first direct memory access control device A signal is output from the first direct memory access control device that specifies a zone of the main memory to which data is to be transferred, and when the signal is not activated, the second direct memory access control device is connected only to the device. a zone designation line set to a state instructing data transfer by the zone designation line; and a circuit that connects the data bus and the main memory with a length of one word when an arbitrary zone designation signal is output to the zone designation line. , a circuit that outputs an access permission signal to a corresponding zone of the main memory based on the zone designation signal; and a second direct memory access control device in accessing the main memory by the second direct memory access control device. A data transfer system comprising: a circuit that connects the data bus and the main memory with a partial word width using address information output from a device to the memory address bus.