JPH04337851A - Memory access system - Google Patents

Abstract

PURPOSE:To access to bit block data as if one piece of bit block data exists for one word with efficiently utilizing a memory by permitting CPU to access to a virtual address and permitting an address/data conversion device provided between CPU and the memory to convert an address and data. CONSTITUTION:When CPU 1 requests memory access to the address/data conversion device 4, the device judges the accessed address is within a virtual memory area or not from a virtual memory area head address 15 and the number of bit block data. When the address is beyond the virtual memory area as the result of judgement, the device 4 directly connects the address buses and the data buses of CPU 1 and the memory 7 and reads word data. When the request of access is the writing of data, it is written into a bit block data position concerned in word data which is read.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access method for a computer system in which the bit length of memory for one address is fixed, and more particularly to a bit-based memory access method.

0002

2. Description of the Related Art Conventionally, when handling data with a bit length less than one word (bit block data), one method has been used: one data is assigned to one word, or one word is divided into bit block data, and one A method was used in which multiple pieces of data were assigned to one word, the CPU accessed the data in units of one word, and the necessary data was retrieved by bit manipulation.

0003

The above-described method of allocating one piece of data to one word has the disadvantage that there are unused bits in one word, resulting in wasted memory. Also, one word can be divided into bit size and
The method of partitioning data and allocating a plurality of data to one word has the disadvantage that the CPU must perform bit operations when accessing the data.

An object of the present invention is to allow a CPU to access bit block data on a memory by accessing a virtual memory area, as if there is one bit block data per word. The purpose of this invention is to provide a memory access method that allows

[0005]

[Means for Solving the Problems] The memory access method of the present invention consists of a CPU, a memory, and a bus that connects these two. In a computer system where the bit length of memory corresponding to one address is fixed (hereinafter, the bit length of this memory division is referred to as one word), the data size is data of a specific bit length less than one word (hereinafter, this bit length is referred to as one word). The memory is divided by the starting address of the memory where only the bit block data is collected (hereinafter, this address is called the starting address of the bit block data), the bit block data is
An address/data conversion device having dedicated registers for setting the bit length of data, the number of bit block data, and the start address of the virtual memory area is installed on the address bus and data bus between the CPU and the memory. When there is a memory access request from the CPU, this address/data conversion device determines whether the address to be accessed is within the virtual memory area from the virtual memory area start address and the number of bit block data, If the address to be accessed is outside the virtual memory area, the address bus and data bus of the CPU and the memory are directly connected, and if the address to be accessed is within the virtual memory area, the address of the word containing the corresponding bit block data is used. The word data of the generated address is read out, and if the access request from the CPU is for reading data, bit manipulation is performed, and bit block data is extracted from the read word data and the data bus is connected to the data bus. and if the access request from the CPU is to write data, the CPU
The CPU receives the data that U wants to write from the data bus, performs bit operations on this data, writes it to the corresponding bit block data position in the read word data, and writes the modified word data to the memory. The bitblock data is accessed such that there is one bitblock data per word.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, which is comprised of a CPU 1 of a computer system, an address/data conversion device 4, and a memory 7 of this computer system. The address/data conversion device 4 includes a bit block data start address register 12, a bit block data bit length register 13, a bit block data start address register 12, a bit block data bit length register 13, a bit block data start address register 12, a bit block data bit length register 13,
It has a data number register 14 and a virtual memory area start address register 15. Further, the data/address conversion device 4 is connected to the CPU 1 via an address bus 2 and a data bus 8, and has an address buffer 3 and a data buffer 9 at the connection portion. Similarly, the data/address conversion device 4 is connected to the memory 7 via an address bus 6 and a data bus 11, and has an address buffer 5 and a data buffer 10 at the connection portion.

FIG. 2 shows this address/data conversion device 4.
shows a conceptual diagram of the operation when converting the address to be accessed. In this example, there are four bit blocks in one word.
There is data, and the bit block data is 7a, 7
Since there are eight pieces of data b, 7c, . . . 7e, the number of bit block data in the bit block data number register 14 is eight. Further, FIG. 3 shows a conceptual diagram of the operation when this address/data conversion device converts data to be accessed. When reading bit block data, CPU1
accesses the virtual memory area. CPU
The address/data conversion device 4 receives the access address from the address bus 2 into the address buffer 3 from the CPU 1 via the address bus 2, and determines whether the address to be accessed by the CPU 1 is greater than or equal to the value of the virtual memory area start address register 15, and if the address is the value of the virtual memory area start address register 15. 15 plus the value of bit block data number register 14. If it is outside the virtual memory area, the address of address bus 2 on the CPU 1 side and memory 7 side is checked. The bus 6, the data bus 8 on the CPU 1 side, and the data bus 11 on the memory 7 side are each directly connected. If the address accessed by CPU 1 is within the virtual memory area, first determine what bit block data CPU 1 is attempting to access from the difference between the address accessed by CPU 1 and the value of the virtual memory area start address register 15. demand. Next, the number of bit block data contained in one word is calculated from the bit block data bit length register 13. For example, if one word is 16 bits and the block data bit length is 4, there will be 4 bit block data in one word.

Based on the number of the bit block data that the CPU 1 is trying to access and the number of bit block data included in one word, the address data conversion device 4 determines whether the bit block data that the CPU 1 is trying to access is a bit block data. By calculating the number of words contained in the data from the first address and adding this result to the value of the bit block data start address register 12, the address of the word containing the corresponding bit block data is generated, and the address buffer is 5 and instructs the memory 7 to read it. The memory 7 sends the word data of the designated address to the address/data conversion device 4 via the data bus 11. address·
The data conversion device 4 converts the word data into the data buffer 1.
0, and extract a bit block from that word data.
Take out the data and write it to the data buffer 9. At this time, if the digit position of the bit block data is not the least significant digit, the address/data converter 4 aligns the bit block data to the least significant digit as shown in FIG. CPU1
reads the bit block data by reading the contents of data buffer 9 via data bus 8.

When writing bit block data, CPU 1 accesses the virtual memory area. Similar to when reading data, the address/data conversion device 4 determines whether the address accessed by the CPU 1 is within the virtual memory area, and if it is outside the virtual memory area, the address/data conversion device 4 uses the address bus 2 on the CPU 1 side and The address bus 6, the data bus 8 on the CPU 1 side, and the data bus 11 on the memory 7 side are each directly connected. If the address accessed by CPU 1 is within the virtual memory area, the address accessed by CPU 1 and the virtual memory area start address register 15 are stored in the same manner as when reading data.
Find out which bit block data the CPU is trying to access from the difference between this value and 1.
CPU from the number of bit block data contained in a word
Calculate the number of words included in the bit block data that you are trying to access from the bit block data start address, and add this result to the value of the bit block data start address register 12 to access the corresponding bit block data. generate the address of the word containing the data,
By writing to the address buffer 5, word data including the corresponding bit block data in the memory 7 is read into the data buffer 10. Thereafter, the address/data conversion device 4 writes the bit block data written in the data buffer 9 to the corresponding bit block data position in the data buffer 10, as shown in FIG. Instructs to write data.

[0011] This will be explained in detail using FIG. CPU
1 is the 5th bit block data 7f counting from 0
When reading, the CPU 1 accesses the address obtained by adding "5" to the value of the virtual memory area start address register 15. The address data conversion device 4 is a CPU
The address accessed by 1 must be greater than or equal to the value of the virtual memory area start address register 12 and less than the value of the virtual memory area start address register 12 plus the value "8" of the bit block data number register 14. This recognizes that the access is to the virtual memory area.

[0012] Next, the address to be accessed by CPU1,
From the difference with the value of virtual memory area start register 15,
It is recognized that the CPU 1 is about to access the fifth bit block data 7f. Based on the bit block/data bit length register 13 and the bit length of one word, the address/data conversion device 4 determines that the bit block data 7f that the CPU 1 is trying to access is the first word counting from the bit block data start address 0. , and reads the word data at the address where "1" is added to the bit block data start address register 12. Next, the read digit position is aligned to the lowest digit and passed to the CPU 1.

When the CPU 1 rewrites the third bit block data 7d counting from 0, the CPU 1 sets the value of the virtual memory area start address register 15 to "3".
” is added to the address. The address/data conversion device 4 checks whether or not the access is to the virtual memory area in the same way as when reading data. register 15
CPU1 detects the third bit block from the difference from the value of
Recognize that you are trying to access data. Based on the bit block/data bit length register 13 and the bit length of one word, the address/data conversion device 4 determines that the CP
Knowing that the bit block data 7d that U1 is trying to access is included in the 0th word of the bit block data start address, the word data indicated by the bit block data start address register 12 is read out.

Next, C in the read word data
The bit block data designated by PU1 is updated with the data that CPU1 intends to write, and the updated word data is written to the original area from which it was read. According to the above procedure, the CPU 1 accesses the bit block data on the memory 7 by accessing the virtual memory area, as if there is one bit block data per word.

[0015]

Effects of the Invention As explained above, the present invention allows the CPU to access a virtual address and converts the address and data using an address/data conversion device provided between the CPU and the memory, thereby saving memory. bitblock data can be accessed as if there was one bitblock data per word, without having to do so or being aware of the actual address or bit position of the bitblock data. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a computer system using an address/data conversion device of the present invention.

FIG. 2 is a conceptual diagram of the operation when the address/data conversion device of this embodiment converts an accessed address.

FIG. 3 is a conceptual diagram of the operation when the address/data conversion device of this embodiment converts data to be accessed.

[Explanation of symbols]

1 CPU 2 Address bus 3 Address buffer 4 Address/data conversion device 5 Address buffer 6 Address bus 7 Memory 8 Data bus 9 Data buffer 10 Data buffer 11 Data bus

Claims (1)

[Claims] [Claim 1] It consists of a CPU, a memory, and a bus that connects these two, and an address indicating a position in the memory area is assigned to the memory, and the bit length of the memory corresponding to one address is fixed. In a certain computer system (hereinafter, the bit length of this memory division is referred to as 1 word),
The memory is divided into data with a specific bit length less than one word (hereinafter, this data will be referred to as bit block data), and the start address of the memory where only bit block data is collected (hereinafter, this address will be referred to as The above-mentioned address/data conversion device has dedicated registers for setting the start address of the bit block data), the bit length of the bit block data, the number of data of the bit block data, and the start address of the virtual memory area. This address/data conversion device is inserted on the address bus and data bus between the CPU and the memory, and when there is a memory access request from the CPU, it converts the virtual memory area start address and bit block.
It is determined whether the address to be accessed is within the virtual memory area based on the number of data, and if the address to be accessed is outside the virtual memory area, the CPU is directly connected to the address bus and data bus of the memory, and the address to be accessed is determined. If is within the virtual memory area, generate the address of the word containing the corresponding bit block data, read the word data of this generated address, and if the access request from the CPU is to read data, perform bit manipulation. bit block data is extracted from the read word data and transmitted to the CPU using the data bus;
If the access request from U is to write data,
The CPU receives the data to be written from the data bus, performs bit operations on this data, writes it to the corresponding bit block data position in the read word data, and writes the modified word data to the memory. A memory access method characterized by accessing bit block data such that one bit block data exists for each word in a CPU.