JP2706082B2 - Address bus control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address bus control method, and more particularly, to a data processing system having a bus configuration of a plurality of buses having different address bit widths. The present invention relates to an address bus control method for performing data transfer between devices.

[Conventional technology]

In recent years, the performance of microprocessors has been improved, and the bit width of address data has been expanded, so that the address space handled by the microprocessor has become extremely large. Recently, a bit width of 32-bit address data handled by a microprocessor has appeared. In such a 32-bit address microprocessor, 32
The area of the address space that can be specified from the bit address data is 4 giga (4G), which is very large. Such a large address space area is used, for example, as a memory space for specifying memory data and an input / output space for specifying an input / output data area for an input / output device.

When a data processing system is configured using such a high-performance microprocessor, the address space of a 32-bit address is too large for a normal input / output device group. For this reason, the bus configuration of a data processing system using a high-performance microprocessor is a bus (memory bus) connecting between the microprocessor and the memory.
And a bus (system bus) connecting the microprocessor and the input / output device group. The bit width of the address bus of the system bus to which the input / output device group is connected is Has a smaller bit width (28-bit address) than the bit width (32-bit address) of the address bus of the memory bus to which it is connected.

As described above, in a data processing system mainly composed of a high-performance microprocessor, the bus configuration includes a bus (memory bus) between the microprocessor and the memory.
, A bus (system bus) between the microprocessor and the input / output device group, and a driver bus interposed between these buses.

By the way, in a data processing system having a plurality of buses, an input / output device to be connected to a system bus connecting an input / output device group is developed in accordance with various conventional microprocessors having an address space with addresses of various bit widths. Some I / O devices have been disabled. This includes an input / output device having an address bit width smaller than the address bit width (28 bit width) of the system bus having a small address bit width. When connecting an I / O device with such a small address bit width to the system bus, a bit width mismatch occurs in the connection of the address bus, and smooth data transfer must be performed for this type of I / O device. Can not.

In this way, for the mismatch between the address bit width of the input / output device to be connected and the bit width of the address bus, for example, a bank setting register is provided to compensate for the lack of bits in the address bit width of the address bus and perform matching. There is a way.

Note that, in a multiple bus configuration, the bank setting register compensates for the shortage of the address bit width of the address bus, and the address bit width is matched.
There is an address bus control device as described in JP-A-60-235268.

[Problems to be solved by the invention]

By the way, when input / output devices having different address bus bit widths coexist on the system bus and transfer data between them, if the address bit widths are inconsistent, the following problem occurs. In other words, the input / output device (slave device) on the side that receives the transferred data
In the case where the bit width of the address bus of the slave device is small, the slave device cannot sufficiently decode the address data on the system bus.
The address space of the transferred address data cannot be mapped. Therefore, data cannot be transferred from a processor that transmits data or an input / output device (master device). If the bit width of the address bus of the input / output device (master device) on the side transmitting the data to be transferred is small, the master device dynamically selects a memory bus and a system bus having different address bus bit widths, Data transfer by DMA (Direct Memory Access) cannot be performed arbitrarily. As described above, there is a problem that input / output device groups having different address bus bit widths cannot coexist on a common system bus.

The present invention has been made to solve the above problems.

An object of the present invention is to enable an I / O device group having different address bus bit widths to be commonly connected to a system bus, and to allow an I / O device group having different address bus bit widths to coexist. It is to provide a control method.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

In order to achieve the above object, in the present invention, a first bus to which a processor and a memory are connected, and an input / output device group having an address bit width smaller than the address bit width of the first bus are connected. In a data processing system including a second bus and a bus control unit for performing bit width matching control of addresses between the buses, the bus control unit determines an access request generation source, and responds to the access request. Address width control signal generating means for generating an address width control signal; and additional address bit data to be added to the address data of the input / output device are stored in correspondence with input / output devices having different address bit widths. Bus address adding means for selecting and sending the additional address bit data to be added by the bus control unit, wherein the bus control unit Depending on the content of the access request, additional address bit data is added to the address data from the access request source on the bus, or upper address bit data of the address data of the access request source on the bus is removed, and It is characterized by transmitting address data matching the address bit width of the address request destination.

[Action]

According to the means, the bus control unit is provided with the address width control signal generating means and the bus address adding means. The address width control signal generating means determines an access request source and generates an address width control signal according to the access request. The bus address adding means stores the additional address bit data to be added to the address data of the input / output device corresponding to the input / output devices having different address bit widths, and adds the additional address bit data to be added by the address width control signal. Select and send.

When the address width control signal generating means determines the access request source and determines that the access request source is the processor, the first
The input / output device (slave device) of the access request destination is determined based on the address data output on the bus (memory bus), and an address bit width control signal corresponding to the address bit width is output. When the access request source is determined to be an input / output device, the address bit width of the access request source input / output device (master device) is determined from the content of the access request, and is output to the second bus (system bus). Based on the address data, an access request destination is determined, and an address bit width control signal corresponding to the address bit width is generated.

The bus address adding means stores additional address bit data to be added to the address data of the input / output device in correspondence with the input / output devices having different address bit widths. The additional address bit data to be added is selected and transmitted by the control signal.

In a data processing system, when an input / output device or a processor connected to a bus sends an access request,
The bus control unit determines an access request source by an address width control signal generation unit, generates an address width control signal, controls the bus address addition unit based on the address width control signal, and controls the bus address addition unit from the access request source on the bus. The additional address bit data is added to the address data, or the upper address bit data of the address data from the access request source on the bus is removed, and the address data of the access request source is matched with the address bit width of the access request destination. It is sent out on the bus as address data. This allows
The address data transmitted to the access request destination is transmitted on the bus as an address bit width corresponding to the address bit width of the access request destination.

This allows a plurality of I / O devices with different address bit widths to be connected to the bus, and data transfer from the processor and DMA data transfer from the I / O device to be performed by buses such as the memory bus and the system bus used between the I / O devices. Can be dynamically switched. Therefore, a group of input / output devices having different address bit widths can coexist on a common system bus, and data can be smoothly transferred between buses having different address bit widths. Therefore, for example, a data processing system can be configured in which a new processor having an extended address space is combined with a conventional input / output device group having an address space narrower than that of the processor.

〔Example〕

Hereinafter, an embodiment of the present invention will be specifically described with reference to the drawings.

In all the drawings for describing the embodiments, the same elements are denoted by the same reference numerals, and a repeated description thereof will be omitted.

FIG. 1 is a block diagram showing an overall configuration of a data processing system according to one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a processor having a 32-bit address (CP
U), 2 is a memory, 3 is a bus control circuit, 4 is a master device of an I / O device using a 28-bit address, 5 is a master device of an I / O device using a 24-bit address, 6 is 28
Slave device of I / O device using bit address,
Reference numeral 7 denotes a slave device of an input / output device using a 24-bit address. A memory bus 8 has a 32-bit address. The processor 1 and the memory 2 are connected to the memory bus 8. 9 is a 28-bit address system bus,
10 is an upper 5 bit address bus of the system bus 9, 11
Is an address bus of the remaining lower 23 bits of the system bus 9. The system bus 9 is divided into an upper 5 bit address bus 10 and a lower 23 bit address bus 11 so that the system bus 9 can be used as a bus to which a 24-bit address input / output device is connected. In the input / output device group connected to the system bus 9, input / output devices (master device 4 and slave device 6) having a 28-bit address are directly connected to the system bus 9. That is, the upper 5 bits of the address of the input / output device are connected to the address bus 10, and the lower 23 bits of the address of the input / output device are connected to the address bus 11. A 24-bit address input / output device (master device 5, slave device 7) has the lower 23 bits of the address connected to the lower 23 bits address bus 11 and the 23rd address of the highest address.
The bit is connected to a separately provided 23rd bit address signal line 11a for use as a path control signal described later. 1
Reference numeral 2 denotes a DMA request signal line which indicates a DMA request from the master side input / output device to be input to the bus control circuit 3; 13 indicates a 28-bit address DMA request signal which indicates a DMA request from the master device 4 having a 28-bit address; Reference numeral 14 denotes a 24-bit address DMA request signal indicating a DMA request from the master device 5 having a 24-bit address. Reference numeral 15 denotes a path control signal for designating a path to be input to the bus control circuit 3, which is address data of the 23rd bit address signal line 11a, which is the most significant bit of a 24-bit address input / output device. Reference numeral 16 denotes an access control signal line from the bus control circuit 3 to the slave-side input / output device, reference numeral 17 denotes a 28-bit address access control signal to the slave device 6 having a 28-bit address, and reference numeral 18 denotes a slave device having a 24-bit address. 7 is a 24-bit address access control signal.

FIG. 2 is a block diagram showing a configuration of the bus control circuit 3 of FIG. In FIG. 2, 8 is a memory bus, 9 is a system bus, 10 is an upper 5 bit address bus, 11 is a lower 23 bit address bus, 12 is a DMA request signal line, and 13 is 28
Bit address DMA request signal, 14 is 24-bit address DMA
Request signal, 15 is a pass signal line, 16 is an access control signal line,
Reference numeral 17 denotes a 28-bit address access control signal, and reference numeral 18 denotes a 24-bit address access control signal, which are the same elements as those in FIG. 19 is an address bus control circuit,
20 is a bus address adding circuit, 21 is a decoder, 22 is a DMA permission signal output from the bus control circuit 19, 23 is a DMA request control signal, and 24 is an access path control signal. 25 is a selector, 26 is a flip-flop indicating that the address bit width is 28 bits, 27 is a flip-flop indicating that the address bit width is 24 bits, 28 is connected to the data bus from the processor 1. Data line, 29
Is a flip-flop for forming a setup time of address data for a signal transmitted to the system bus 9 and the access control signal line 16. Numeral 30 denotes an AND gate for transmitting a 28-bit address access control signal 17, 31 denotes a NOT gate, 32 denotes an AND gate for transmitting a 24-bit address access control signal 18, and 33 denotes an upper 5 bits of the system bus 9 from the address bus 10. It is a decoder that decodes a signal. The logic "1" signal is output from the decoder 33 when the address space for the slave device 7 having a 24-bit address is designated as the access request destination.
34 is a NOT gate. 35 is a driver gate for connecting the address bus 11 of the lower 23 bits of the system bus 9 to the memory bus 8, 36 is an enable signal for controlling the driver gate, and 37 is a path control signal 15 for designating a path, outputting logic "1". The driver gate 38 transfers address data of the 27th to 23rd bits of the memory bus 8 to the system bus 9
A driver gate 39 for connecting the address data of the 22nd to 0th bits of the memory bus 8 to the address bus 11 of the lower 23 bits of the system bus 9; The driver gate 40 is a bit width designation control signal sent from the selector 25, and is a signal indicating whether the address bit width of the master device that has permitted the DMA request is 28 bit width or 24 bit width.

Address data on the memory bus 8 is input to the address bus control circuit 19 via the decoder 21, and a DMA request signal is input from the DMA request signal line 12. Based on these signal inputs, the address bus control circuit 19 determines the access request source for loading data on the bus, and controls the address bit width when the address bit width of the address request destination specified by the address data is different. Is transmitted. That is, the address bus control circuit 19 determines the DMA request based on the content of the access request, and
A request control signal 23 and an access path control signal 24 are output to control the bus address addition circuit 20, various gates, and the like. The bus address addition circuit 20 stores additional address data that satisfies the bit difference between the bus address data in correspondence with input / output devices having different address bit widths, and according to a control signal from the address bus control circuit 19, The additional address data is transmitted on the memory bus 8 and the system bus 9. In addition, various gates and the like connect the address bus between the memory bus 8 and the system bus 9 to match the bit width of necessary address data.

FIG. 3 is a block diagram showing a configuration of the bus address adding circuit 20 of FIG. In FIG. 3, 8 is a memory bus, 10 is an upper 5-bit address bus of the system bus 9, 15 is a path control signal, 22 is a DMA enable signal, 28 is a data line connected to the data bus from the processor 1, Reference numeral 36 denotes an enable signal for the driver gate 35, and reference numeral 40 denotes a bit width designation control signal, which is the same element as in FIGS. 41 and 42 are NAND gates, 43 is a NOT gate, and 44 is a selector. Reference numeral 45 denotes a decoder. The decoder 45 detects when address data designating the DMA window space of the memory bus 8 is transmitted to the upper 5 bits of the address bus 10 of the system bus 9. Reference numeral 46 denotes a first flip-flop group. The first flip-flop group 46 stores additional address data having a 9-bit width to be added to the address data transmitted to the memory bus 8. Reference numeral 47 denotes a second flip-flop group, and the second flip-flop group 47 includes:
The additional address data having a 5-bit width to be transmitted to the upper 5-bit address bus 10 of the system bus 9 is stored. Numeral 48 denotes a driver gate for transmitting the address additional data of the first flip-flop group 46 to the memory bus 8, and numeral 49 denotes a driver gate for transmitting the address additional data of the second flip-flop group 47 to the upper 5-bit address bus 10. .

Next, the operation of the device configured as described above will be described. When an access request from an input / output device group or a processor connected to the bus occurs, the bus control circuit 3 performs an address bus control operation according to the content of the access request.

First, access from the processor 1 to the slave devices 6 and 7 will be described with reference to FIGS.

In FIG. 1, when a processor 1 having a 32-bit address outputs 32-bit address data to a memory bus 8, a bus control circuit 3 performs an address bus control operation, and a slave device 6 or a 24-bit address having a 28-bit address. A control operation for determining an access path of the address to the slave device 7 is performed.

Next, referring to FIG. 2 showing the configuration of the bus control circuit 3, 32-bit address data output from the processor 1 to the memory bus 8 is decoded by the decoder 21. The decoded address of the decoder 21 is a slave device.
If it is 6,7, the decoded output is sent to the address bus control circuit 1.
Output to 9. The address bus control circuit 19 determines the presence or absence of a DMA request signal from the DMA request signal line 12, and when there is no DMA request signal, accesses using the bus to secure an access path to the slave devices 6 and 7. An access path control signal 24 indicating that the operation is performed. The access path control signal 24 is supplied to the driver gates 37, 38,
39 to enable the driver gates 37, 38, 39. As a result, the driver gate 38 outputs the address data from the 27th bit to the 23rd bit of the memory bus 8 to the upper 5 bits of the address bus 10 of the system bus 9. The driver gate 39 outputs address data from the 22nd bit to the 0th bit of the memory bus 8 to the address bus 11 of the lower 23 bits of the system bus 9. The driver gate 37 outputs the 23rd bit address data of the memory bus 8 to a 23rd bit address signal line 11a separately provided in order to give the highest address to the slave device 7 of the 24 bit address. The 5-bit address data output from the driver gate 38 to the address bus 10 is
The data is input to the decoder 33 and decoded. The decoder 33 decodes the address data on the address bus 10 and outputs a logical "1" signal when the 5-bit address data indicates the slave device 7.

On the other hand, the access path signal 24 is input to the flip-flop 29, and is output from the flip-flop 29 as an access control signal after securing setup time for outputting address data on the bus by the driver gates 37, 38, and 39. . When the output from the decoder 33 is a logical "1" according to the data on the address bus 10, the output of the flip-flop 29 is output from the AND gate 32, and is output as the 24-bit address access control signal 18 for selecting the slave device 7. Is output. The output from the decoder 33 is logic “0”.
In the case of, the output of the flip-flop 29 is output from the AND gate 30 by the output of the NOT gate 31, and the 28-bit address access control signal for selecting the slave device 6
Output as 18.

In this way, the bus control circuit 3 determines the access request of the access request source from the address data output to the memory bus 8, selects the access request destination slave device, and outputs the access control signal. The address bit width of the different address data for each bus depends on the driver gate 37, 38,
A slave device having a 28-bit address different in address width from the processor 1 having a 32-bit address, matched by 39
The address bus control is performed so that the 6- or 24-bit address slave device 7 can be accessed.

Next, an access operation from the input / output device will be described. First, a master device 5 using a 24-bit address
A description will be given of the data transfer by DMA from.

FIG. 4 shows a master device 5 using a 24-bit address.
FIG. 3 is a diagram for explaining an address bus control operation when data is transferred by DMA to a memory 2 connected to a memory bus 8 having a 32-bit address. In FIG. 4, reference numeral 50 denotes 24-bit address data output from the master device 5. The 24-bit address data 50 is a path control signal
Address data of the most significant bit MT23, which is 15, the lower 23 bits of address data that specifies the transfer destination address space
It consists of address data of M22 to M0. Reference numeral 51 denotes additional address data MF8 to MF0 having a 9-bit width stored in the flip-flop group 46 (FIG. 3). 52 is a 32-bit address signal MA31 sent to the memory bus 8
~ MA0 is shown.

Referring to FIG. 1, FIG. 2, FIG. 3, and FIG.
The DMA is transferred from the master device 5 using the 24-bit address to the memory 2 connected to the memory bus 8 with the 32-bit address.
An address bus control operation in the case of performing data transfer according to the first embodiment will be described.

First, reference is made to FIG. When performing data transfer by DMA, the master device 5 having a 24-bit address sends a 24-bit address DMA request signal 14 to the bus control circuit 3 and sends the lower 23 bits of address data (M22 to M0:
An address signal 50 in FIG. 4 is transmitted, and the most significant bit of address data (MT23: address signal 50 in FIG. 4) is transmitted to the bus control circuit 3 as a path control signal 15. Next, reference is made to FIG. When the 24-bit address DMA request signal 14 and the path control signal 15 are sent to the bus control circuit 3, the address bus control circuit 19 determines the use of the bus based on the 24-bit address DMA request signal 14, and enables the DMA. A signal 22 and a DMA request control signal 23 are output. The DMA request control signal 23 becomes logic "1" when detecting the 28-bit address DMA request signal 13, and becomes logic "0" when detecting the 24-bit address DMA request signal 14. Here, 24
Since bit address DMA request signal 14 has been detected, D
A logical “0” signal is output as the MA request control signal 23 and is supplied to the selector 25. As a result, the selector 25 selects a signal of the flip-flop 27 set in advance from the data bus (not shown) of the processor 1 via the data line 28, and sets the signal as the bit width designation control signal 40 of the output of the selector 25. Outputs a logical “1” signal indicating that the address bit width of the master device that has detected the DMA request is 24 bits, and is supplied to the bus address addition circuit 20.

Next, refer to FIG. In the bus address adding circuit 20 shown in FIG.
Is input to the selector 44 and the NAND gate 42. The selector 44 selects the path control signal 15 based on the logic “1” signal. The path control signal 15 is a signal of the most significant bit (MT23: address signal 50 in FIG. 4) of address data output from the master device 5 having a 24-bit address, and the master device 5 accesses the memory bus 8 by DMA. In this case, a logical “0” signal is transmitted as the path control signal 15. When the path control signal 15 is given as a logical “0” signal, the logical “0” signal of the path control signal 15 is negated.
It becomes logic “1” by 43 and is added to the NAND gate 41. NAND gate 41 to which DMA enable signal 22 is supplied
Outputs the enable signal 36 in response to the logical "1" signal from the NOT gate 43 and enables the driver gate 48. As a result, the address data (MF0 to MF8: fourth data) stored in advance in the 9-bit flip-flop group 46 from the data bus of the processor 1 via the data line 28 to a predetermined value.
The additional address data 51) shown in the figure is transmitted to the memory bus 8 as the address data of the upper 9 bits of the memory bus 8.

On the other hand, the driver gate 35 (FIG. 2) is enabled by the output of the enable signal 36, and the 23-bit address data (M22 to M0: address signal 50 in FIG. 4) of the master device 5 transmitted to the address bus 11 is transmitted. ) Is the memory bus 8
From the 22nd bit to the 0th bit address bus, and becomes address data of lower 23 bits (MA22 to MA0: address signal 52 in FIG. 4). Therefore, as shown in FIG. 4, it is stored in advance in the 23-bit address data (M22 to M0 of the address signal 50) of the address bus 11 in accordance with the instruction of the path control signal 15 (MT23 of the address signal 50). 9-bit address data (MF8 to MF0) are concatenated, and 32
The data is transmitted to the memory bus 8 as bit address data (MA0 to MA31). That is, the bus control circuit 3 responds to the address data 50 (MT23, M22 to M0) from the master device 5 using the 24-bit address, and transmits the 32-bit address data 52 (MA31) to the memory bus 8.
To MA23, MA22 to MA0), the memory bus 8 can be addressed as a 32-bit address, and data can be transferred between the master device 5 and the memory 2 by DMA.

Next, an address bus control operation when the 24-bit address master device 5 performs DMA data transfer to the 28-bit address slave device 6 connected to the system bus 9 will be described.

FIG. 5 is a diagram for explaining the operation of the address bus control. In FIG. 5, 50 is output by the master device 5.
It shows 24-bit address data. The 24-bit address data 50 is the most significant bit serving as the path control signal 15.
It is composed of address data of MT23 and address data of lower 23 bits M22 to M0 for designating a destination address space. Reference numeral 53 denotes 5-bit additional address data SF4 to SF0 stored in the flip-flop group 47 (FIG. 3). Reference numeral 54 denotes 28-bit address data SA27 to SA0 transmitted to the system bus 9.

Referring to FIG. 5, master device 5 having a 24-bit address
A description will be given of an address bus control operation when DMA data transfer is performed to the slave device 6 connected to the system bus 9 having a 28-bit address.

This address bus control operation is the same as the above-described address bus control operation when the master device 5 performs DMA data transfer to the memory bus 9. That is, the system bus 9
, The path control signal 15 of the most significant bit of the address data output from the master device 5 is a logical "1" signal. The address data added by the logic “1” signal of the path control signal 15 is
5-bit additional address data SF4 to S stored in
It becomes F0. Therefore, the address data transmitted to the system bus 9 is different from the 23-bit address data (M22 to M0) transmitted from the master device 5 by the path control signal 15 (MT2
5-bit additional address data (S
F4 to SF0) are the concatenated 28-bit address data (SA27 to SA23, SA22 to SA0).

Referring to FIG. 1, a master device 5 is a slave device 6 connected to a system bus 9 having a 28-bit address.
When performing data transfer by DMA, a 24-bit address DMA request signal 14 is sent to the bus control circuit 3 and the lower 23 bits of address data (M22 to M22) are sent to the address bus 11.
0: FIG. 5). Also, the bus control circuit 3 sends the address data of the most significant bit of the address data (MT23:
Is transmitted as the path control signal 15. Bus control circuit 3
In the same manner as in the case of the DMA data transfer via the memory bus 8 described above, the bus address addition circuit 20 sends the logic "1" signal of the DMA enable signal 22 and the logic "1" signal of the bit width designation control signal 40 to each other. Is given. In the bus address adding circuit 20 shown in FIG.
When the signal is input to the selector 44 and the NAND gate 42, the selector 44 selects the path control signal 15 side by the logic "1" signal. As a result, the path control signal 15 is input to the NAND gate 42 and the NOT gate 43. In the case of DMA data transfer via the system bus 9, since the logical “1” signal is output as the path control signal 15, the output of the NOT gate 43 becomes logical “0”, and the enable signal 36 is output from the NAND gate 41.
Is not sent. The NAND gate 42 enables the driver gate 49 by the logic "1" signal of the bit width designation control signal 40, the logic "1" signal of the path control signal 15, and the logic "1" signal of the DMA enable signal 22 applied to the NAND gate 42. And As a result, the address data (SF4 to SF0: FIG. 5) stored in the flip-flop group 47 at a predetermined value in advance.
Is transmitted to the address bus 10 via the driver gate 49.

On the other hand, the address bus of the lower 23 bits of the system bus 9
11, address data (M22 to M0: FIG. 5) is transmitted from the master device 5, and in conjunction with this, the system bus 9 (address bus 10, address bus 11) transmits a 28-bit address. The address data (SA27 to SA0) is transmitted, and the addressing of the slave device 6 of the 28-bit address is performed.

Thus, an address bus control operation is performed when DMA data transfer is performed between the master device 5 having a 24-bit address and the slave device 6 having a 28-bit address. Note that the access control signal to the slave device 6 is determined by the decode output of the decoder 33 that decodes the address data sent to the address bus 10 and the output of the flip-flop 29, and the AND gate 30, the negation gate 31, and the AND gate 32 are output. In the logical operation, the 28-bit address access control signal of the corresponding access control signal from the access control signal line 16
17 is sent out.

Next, the master device 4 using the 28-bit address
An address bus control operation when performing data transfer by DMA to the memory 2 connected to the memory bus 8 will be described.

FIG. 6 is a diagram for explaining the address bus control operation. In FIG. 6, reference numeral 52 denotes 32-bit address data MA31 transmitted to the memory bus 8 via the bus control circuit 3.
-MA23, MA22-MA0. Reference numeral 55 denotes 28-bit address data M27 to M23, M22 to M22 output from the master device 4.
M0 is shown. The 28-bit address data 55 includes upper 5 bits of address data M27 to M23 transmitted to the upper 5 bits address bus 10 of the system bus 9 and lower 23 bits transmitted to the lower 23 bits address bus 11 of the system bus 9.
It is composed of 23-bit address data M22 to M0. Reference numeral 56 denotes 9-bit data MF'8 to MF'0 stored in the flip-flop group 46 (FIG. 3).

Referring to FIG. 1, FIG. 2, FIG. 3, and FIG.
The DMA is transferred from the master device 4 using the 28-bit address to the memory 2 connected to the memory bus 8 having the 23-bit address.
An address bus control operation when data transfer is performed will be described.

Please refer to FIG. The master device 4 includes the bus control circuit 3
Sends a 28-bit address DMA request signal 13 to the system bus 9 and sends 28-bit address data (M27 to M0: FIG. 6).
Is sent. That is, upper 5 bits of address data (M27 to M23) are transmitted to the address bus 10, and lower 23 bits of address data (M22 to M0) are transmitted to the address bus 11.

Next, reference is made to FIG. 28 for the bus control circuit 3
When the bit address DMA request signal 13 is transmitted, the address bus control circuit 19 sends the 28-bit address DMA request signal 13
Thus, the use of the bus is determined, and the DMA enable signal 22 and the DMA request control signal 23 are output. As described above, the DMA request control signal 23 becomes a logical "1" signal when the 28-bit address DMA request signal 13 is detected. Therefore, a logical "1" signal is given to the selector 25, and the selector 25 selects a signal of the flip-flop 26 set in advance from the data bus of the processor 1 via the data line 28. This allows
The address bit width of the master device that sent the DMA request is 28
A logic “0” signal indicating that the bit width
The signal is supplied to the bus address adding circuit 20 as a bit width designation signal 40 via 25.

Next, referring to FIG. 3, the bus address adding circuit 20 shown in FIG.
The signal is input to the selector 44 and the NAND gate 42.
The selector 44 selects a signal from the decoder 45 according to the logic “0” signal. The decoder 45 decodes address data on the address bus 10 and outputs a logical "0" signal when each bit of the address data (M27 to M23) is "0". decoder
When a logical “0” signal is output from 45, the logical “0” signal is applied to the NOT gate 43 via the selector 44 and is applied to the NAND gate 41. The NAND gate 41 to which the DMA permission signal 22 is supplied outputs the enable signal 36 in response to the logical "1" signal from the NOT gate 43 and enables the driver gate 48. As a result, the address data (M
F'8 to MF'0: FIG. 6) are transmitted to the memory bus 8 as the upper 9 bits of address data (MA31 to MA23) of the memory bus 8. On the other hand, the driver signal 35 (FIG. 2) is enabled by the enable signal 36, and the lower 23 bits of the address data (M22 to M0) of the 28-bit address of the master device 4 transmitted to the address bus 11.
Is the lower 23 bits of address data (MA
22 to MA0). Thus, as shown in FIG. 6, the address data 55 (M27 to M23, M22) from the master device 4 using the 28-bit address is stored on the memory bus 9.
.. M0), address data 52 (MA31-MA23, MA22-MA0) of the 32-bit address to the memory bus 8 is formed, and can be addressed as a 32-bit address. 2 can be used to transfer data by DMA.

On the other hand, when the master device 4 performs the DMA data transfer to the input / output device group via the system bus 9, the address bus control circuit 19 A corresponding access control signal is transmitted from the access control signal line 16 by the decoder 33, and the slave device 6 having a 28-bit address is transmitted.
Alternatively, data transfer with the slave device 7 having a 24-bit address is performed.

As described above, the bus control circuit 3 dynamically performs the address bus control operation for matching the bit width of the bus address data according to the content of the access request from the access request source, and the input / output device having the different address bit width. DMA data transfer is performed between the memory and the processor between the groups.

DMA data transfer is performed between each input / output device group, a memory, a processor, and the like via a system bus 9 to which the input / output device groups having different address bit widths are connected. FIG. 7 shows the space allocation of the address space of the system bus 9 specified by the address data of FIG.

FIG. 7 is a diagram showing a map of an address space in the system bus 9. The address space of the system bus 9 starts from the lowest address X “FFFF FFFF” of the 32-bit address (4 GB) address space on the memory bus 8.
256 MB address space (addresses X “F000 0000” to X “F
FFF FFFF ") is mapped as the address space of the 28-bit address of the system bus 9. Of the 256 MB address space mapped on the system bus 9, the highest address X of the mapped address space is mapped.
8 MB address space from “F000 0000” (address X “F00
0 0000 "to X" F07F FFFF ") is a memory bus DMA used when performing DMA data transfer from the master device 4 of the 28-bit address connected to the system bus 9 to the memory bus 8.
Mapped as window space. The remaining address space below it (addresses X “F07F FFFF” to X “FFFF
FFFF ") is a slave device connected to the system bus 9
6 and 7 are mapped as a normal system bus space used when data is transferred from the master device 4. Similarly, the address space used when performing DMA data transfer from the master device 5 of a 24-bit address connected to the lower 23-bit address bus 11 of the system bus 9 is shown in the map on the right side of FIG. As shown,
Of the 16 MB address space of the lower 23-bit address bus 11, the address space of 8 MB from the highest address is mapped as the memory bus DMA window space. The remaining address space of the remaining lower 8 MB is the slave device 7
Is mapped as the system bus space for As shown in FIG. 7, when mapping the address space of the 28-bit address of the system bus 9 to the 32-bit address of the memory bus 8, the address space of the memory bus DMA window used for DMA data transfer is specified. The upper four bits of address data MF8 to MF0 (FIG. 4) and address data MF'8 to MF'0 (FIG. 6) to be added are "1111".

As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various changes can be made without departing from the scope of the invention.

〔The invention's effect〕

As described above, according to the present invention, in a data processing system having a multiple bus configuration, a plurality of input / output devices having different address widths are directly connected to a bus to transfer data from a processor and receive data from an input / output device. DMA data transfer can be performed by dynamically switching a plurality of buses such as a memory bus and a system bus used between input / output devices. Therefore, a group of input / output devices having different address bit widths can coexist on a common system bus, and data can be smoothly transferred between buses having different address bit widths. Therefore, for example, a new processor having an extended address space can be easily combined with a conventional input / output device group having a narrower address space, and a data processing system can be configured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a data processing system according to one embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a bus control circuit in FIG. 1, and FIG. FIG. 4 is a block diagram showing the configuration of the bus address adding circuit shown in FIG. 4, FIG. 4 is a diagram for explaining an address bus control operation from a 24-bit address bus to a 32-bit address bus, and FIG. FIG. 6 is a diagram for explaining an address bus control operation from a bus having a 28-bit address to a bus having a 28-bit address, and FIG. FIG. 3 is a diagram showing a map of an address space in a bus. In the figure, 1 ... processor (CPU), 2 ... memory, 3 ... bus control circuit, 4, 5, 6, 7 ... input / output device, 8 ... memory bus, 9
... system bus, 10, 11 ... address bus, 12 ... DMA request signal line, 13 ... 28-bit address DMA request signal, 14 ... 24-bit address DMA request signal, 15 ... path control signal, 16 ... access control signal line, 17 ... 28 bit address access control signal, 18 ... 24 bit address access control signal, 19 ... address bus control circuit, 20 ... bus address addition circuit, 21 ... decoder, 22 ... DMA enable signal, 23 ... DMA request control signal, 24 ...
Access path control signal, 25 selector, 26, 27 flip-flop, 28 data line, 29 flip-flop, 3
0, 32: AND gate, 31, 34: NOT gate, 33: Decoder, 35: Driver gate, 36: Enable signal, 37, 38,
39: driver gate, 40: bit width designation control signal, 41, 4
2… Nand gate, 43… Negative gate, 44… Selector, 45
... decoder, 46 ... first flip-flop group, 47 ... second
Flip-flops, 48, 49 ... driver gates.

Claims (1)

(57) [Claims] 1. A first device to which a processor and a memory are connected.
, A second bus to which an input / output device group having an address bit width smaller than the address bit width of the first bus is connected, and a bus for performing address bit width matching control between the buses A data processing system comprising: a control unit; an address width control signal generating unit configured to determine an access request source in the bus control unit and generate an address width control signal in response to the access request; Bus address adding means for storing additional address bit data to be added to the data corresponding to input / output devices having different address bit widths, and selecting and transmitting the additional address bit data to be added by the address width control signal. The bus control unit converts the address data from the access request source on the bus according to the contents of the access request from the access request source. It is characterized by adding additional address bit data or removing upper address bit data of an access request source address data on a bus, and sending address data matching the address bit width of the address request destination on the bus. Address bus control method.