JPH01277954A - Shared storage device - Google Patents

Abstract

PURPOSE:To select the word length and the constitution of read data by properly selecting a storage area by a used host device and accessing data having the set word length through a set data bus. CONSTITUTION:When a microprocessor which uses a 16-bit data bus gets the bus right, this state is reported to a memory selecting circuit 23 and a port selecting circuit 24. Further, an address signal is inputted through busses 25 and 26. The circuit 23 selects both memory elements 20a and 20b of a shared memory 20 in this case. When the same address signal is inputted to elements 20a and 20b in this state, data is outputted to an upper byte 16a and a lower byte 16b of the 16-bit data bus through switches 22a and 22b. When an I/O device which uses data having 8-bit word length gets the bus right, the circuit 23 selects the element 20a or 20b. When the address signal is inputted to the memory 20, data is outputted to a data bus 17 from one memory element of the memory 20.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a shared storage device shared by a plurality of host devices.

(Prior Art) A storage device is generally an essential device for an information processing device.

Typically, a storage device made up of a combination of memory elements is controlled by one microprocessor. However, one storage device may be shared by two or more higher-level devices in order to share data or take memory usage efficiency into consideration.

FIG. 2 shows a block diagram of such a conventional memory configuration.

This device is provided with a microprocessor 11, an I10 device 12, a memory control circuit 13, and a data bus switching circuit 14, and a shared memory shared by the microprocessor 11 and I10 device 12 is an upper byte memory. 15a and lower byte memory 15b.

The microprocessor 11 and the data bus switching circuit 14 are connected by an upper byte data bus 16a and a lower byte data bus 16b, and an upper byte memory 15a is connected to the upper byte data bus 16a. A lower byte memory 15b is connected to the data bus 16b. In this example, the upper byte memory 15a and the lower byte memory 15b each have 8
The memory element has a bit configuration, and the upper byte data bus 1
6a and lower byte data bus 16b are both pass lines for transmitting 8-bit data.

On the other hand, an 8-bit data bus 17 is provided to connect the data bus switching circuit 14, the memory control circuit 13, and the factory/○ device 12. Although not shown in this figure, it is assumed that in addition to these data buses, an address bus, a control bus, etc. are provided between each block.

In this device, microprocessor 11 and I10
The device 12 is a data bus 16a.

The upper byte memory 15a and the lower byte memory 15b are accessed while competing for the right to use the bus 16b. This bus control is performed by the memory control circuit 1.
3 will do it. The data bus switching circuit 14 switches the 8-bit data bus 17 to an upper byte data bus 16a or a lower byte data bus 16 according to a certain control.
This is a circuit that switches the connection to connect to b.

It is assumed that various external devices (not shown) are connected to the I10 device 12.

First, the operation when the microprocessor 11 acquires the bus right will be described.

When the microprocessor 11 acquires the bus right, the data bus switching circuit 14 enters a high impedance state. When an address signal is simultaneously output from the microprocessor 11 to the upper byte memory 15a and the lower byte memory 15b, the address signal is sent to these memories through the upper byte data bus 16a and the lower byte data bus 16b.
It becomes possible to access the data. This allows the microprocessor 11 to read and write data with a data length of 8 bits x 2, that is, a total of 16 bits.

On the other hand, when the I10 device 12 acquires the bus right, the data bus switching circuit 14 switches the 8-bit I10 data bus 17 to the upper byte data bus 16a or the lower byte data bus 16, depending on the memory to be accessed.
Connect to b. Then, for example, upper byte data bus 1
Regarding the upper byte memory 15a connected to 6a, 8
Bit data is accessed by I10 device 12 via upper byte data bus 16a.

(Problem to be Solved by the Invention) Incidentally, in such a device, the I10 device 12 essentially has two memories, namely, the upper byte memory 1
Although it is possible to use the upper byte memory 15a and the lower byte memory 15b, in cases where high-speed data access is required, the upper byte memory 15a or the lower byte memory 15b is actually used.
The configuration is such that only one of the memory elements b is accessed.

That is, when attempting to access data randomly, for example, the upper byte memory 15a and the lower byte memory 15
If an attempt is made to access both of the data buses alternately, the data bus switching circuit 14 must perform data bus switching control at high speed, but in reality, this switching speed is extremely slow compared to the data access speed, and the host device A so-called data delay occurs in which the data access does not follow the operation of the data.

On the other hand, due to such considerations, if only one memory element is used by the I10 device 12, the other memory element will be used only by the microprocessor 11, which poses the problem of lower memory usage efficiency. .

The present invention has been made with attention to the above points, and an object of the present invention is to provide a shared storage device that can be used efficiently and flexibly by a plurality of host devices.

(Means for Solving the Problems) A shared storage device of the present invention is connected to a plurality of higher-level devices, a shared memory whose storage area is shared by the plurality of higher-level devices, and an input/output port of the shared memory, a bus right identification signal that identifies which higher-level device is given bus rights to a word-length data bus set for each of the higher-level devices and an address/control bus that controls reading of the shared memory; , a memory selection circuit and a port selection circuit that accept address/control signals, and the memory selection circuit has a memory selection circuit that accepts an address/control signal,
Based on the bus right identification signal and the address signal, the port selection circuit outputs a memory area selection signal for accessing data of a word length set for each of the host devices in a predetermined area of the shared memory; , the input/output port of the shared memory is selectively connected to the data bus based on the bus right identification signal.

The device of the present invention also includes a host device similar to the above, a shared memory, a data bus, and an address signal provided for each of the above-mentioned host devices and output from each of the above-mentioned host devices to control reading of the multi-port shared memory. and an address conversion circuit that performs a predetermined address conversion, and the address conversion circuit converts data of a word length set for each host device into the shared memory for a predetermined area of the shared memory. The present invention is characterized in that an address signal for accessing is selectively outputted to each of the ports.

(Operation) The above device outputs a memory area selection signal to the shared memory based on a bus right identification signal that identifies which host device has acquired the bus right. For example, shared memory is divided into several areas, and if the data length stored in one memory area is 1 unit, if data is read from two areas simultaneously, the data length will be 2 units. , when data is read from four areas simultaneously, access can be performed for a data length of four units. When the shared memory is composed of a plurality of memory elements, a port selection circuit selectively connects the human output port of the shared memory to a data bus provided for each host device.

Furthermore, when using a multi-port memory, the area selection described above is achieved by converting the address signal output from each host device, and using the converted address signal to selectively select each port of the shared memory. This is achieved by accessing.

(Example) Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.

FIG. 1 is a block diagram showing a first embodiment of the apparatus of the present invention.

This device includes a shared memory 2 consisting of two memory elements.
0 is set. This shared memory 20 is, for example,
It is constructed by combining two semiconductor memory elements that can access data with a data length of 8 bits.

Input/output ports 21a, 2 of each memory element 20a, 20b
1b is connected to switches 22a and 22b. And this switch 22a.

The outputs of 22b are connected to the upper byte 16a, lower byte 16b and 8-bit I10 data bus 17 of a 16-bit data bus, respectively. This 16-bit data bus is used, for example, by the microprocessor 11 shown in FIG.
It is assumed that the 8-bit I10 data bus 17 is accessed by the I10 device 12 shown in FIG.

On the other hand, the shared memories 20a and 20b have an address bus 2.
5 is connected. This address bus 25 is also connected to input to the memory selection circuit 23 and port selection circuit 24. A control bus 26 and a bus right identification signal line 27 are connected to the memory selection circuit 23 . The port selection circuit 24 also includes a bus right identification signal line 27.
is connected. .

The memory selection circuit 23 is a circuit that outputs a memory area selection signal 28 that selects one or both of the memory elements constituting the shared memory 20 based on the control signal and bus right identification signal input here. Further, the port selection circuit 24 is a circuit that receives the bus right identification signal and outputs a port control signal 29 for controlling the connection operation of the switch 22a or 22b. Both the memory selection circuit 23 and the port selection circuit 24 are constructed from logic circuits combining gates and the like.

The apparatus having the above configuration operates as follows.

First, when a microprocessor using a 16-bit data bus acquires bus ownership, the memory selection circuit 23 and port selection circuit 24 are notified of this through the bus identification signal line 27. Furthermore, address signals are input from the microprocessor via an address bus 25 and a control bus 26.

In this case, the memory selection circuit 23 selects both memory elements 20a and 20b of the shared memory 20 and makes both accessible. On the other hand, the port selection circuit 24 is connected to the switch 22a.
, 22b of the shared memory 20.
The output port 21a of a is connected to the upper byte 16a of the 16-bit data bus, and
0b output port 21b is connected to the lower byte 16b of the 16-bit data bus. In this state, address bus 2
5, both memory elements 20a, 2 of the shared memory 20
When the same address signal is input to 0b, for example, 8-bit word length data is read from each chip and output to the upper byte 16a and lower byte 16b of the 16-bit data bus via switches 22a and 22b. be done. In this way, 16-bit word length data is accessed.

If the configuration of the 16-bit data bus of the microprocessor is such that the upper byte and lower byte are reversed, the connections between the switches 22a and 22b may be changed so that the input/output port 21a of the memory element 20a of the shared memory 20 is connected to the lower The input/output port 21b of the memory element 20b may be connected to the upper byte 16a.

In this way, the device of the present invention can freely alternately switch the positional relationship between the upper byte and the lower byte by the operation of the port selection circuit 24.

Next, a case will be described in which an I10 device using 8-bit word length data acquires the bus right.

This bus right identification signal is input to the memory selection circuit 23 and the port selection circuit 24 via the bus right identification signal line 27. Further, address signals and control signals are input from the I10 device through the address bus 25 and control bus 26.

The memory selection circuit 23 generates a memory area selection signal 28 according to the content of the address signal, and selects either one of the memory elements 20a or 20b of the shared memory 20. Further, the port selection circuit 24 recognizes that the I10 device has acquired the bus right, and selects the memory element 20a.
, 20b are connected to the switch 22a or 2
A port control signal 29 is output to connect to the 8-bit I10 data bus 17 via 2b.

That is, in this embodiment, input/output ports 21a, 21b of memory elements 20a, 20b of shared memory 20 are both simultaneously connected to 8-bit I10 data bus 17 via switches 22a, 22b.

Here, when an address signal is input to the shared memory 2o through the address bus 25, data is read from one of the memory elements of the shared memory 20, for example, and is output to the 8-bit I10 data bus 17 through the switch 22a or 22b. be done. In this case, the memory element is only selected by the memory area selection signal 28, and neither of the switches 22a and 22b operates at the time of access, so high-speed access is possible.

FIG. 3 shows a block diagram of a second embodiment of the device of the invention.

This device uses a 3-port memory 31 provided with three ports PO-P2.

Traditionally, a well-known type of memory is dual-port memory, but this 3-port memory has almost the same functions, accepting address signals and control signals at three ports PO-P2, and three human output ports. , the data corresponding to that address signal can be accessed. The internal structure of the memory is a single memory,
In reality, the configuration is such that one memory area can be accessed simultaneously from three ports. It is assumed that, for example, 8-bit data is read from each port.

Therefore, when the same address is accessed at the same time, in order to adjust the conflict, a built-in circuit is provided that prioritizes the address signal and control signal input from any one port. The detailed circuit configuration and the like are the same as those of the conventional dual port memory, and a detailed explanation thereof will be omitted.

This circuit is provided with a microprocessor 11, an I10 device 12, and a memory control circuit 13.
6a is connected to port PO, and lower byte data bus 16b is connected to port P1. Further, the control bus 26 of the microprocessor 11 is connected to the port P.
0 and port P1 in parallel. Further, the address bus 25 of the microprocessor 11 is individually connected to the port PO and the port P1 via an address conversion circuit 32.

On the other hand, the data bus 17 and control bus 35 of the memory control circuit 13 are configured to be directly connected to the port P2, and the address bus 34 is configured to be connected to the port P2 via the address conversion circuit 33.

This device operates as follows.

First, in this device, the bus ownership between the microprocessor 11 and the I10 device 12 is not adjusted. As described above, both devices can arbitrarily access data at any timing unless there is a conflict such as accessing data at the same address.

First, when the microprocessor 11 accesses data, an address signal is output to the address bus 25, and a command to access data from ports P1 and PO is issued via the control bus 26. The address conversion circuit 32 converts the address signal into an address signal for port PI and an address signal for port P according to predetermined rules.
Converts it into an address signal for O and outputs it to these ports. The data read by this is transmitted from port PO to upper byte data bus 16a, and from port P1 to port P1.
is read by the microprocessor 11 via the lower byte data bus 16b. This address conversion process will be explained later using FIGS. 4 and 5.

On the other hand, when the I10 device 12 performs an access, its control signal is sent to the port P2 via the control bus 35. Further, the address signal 34 undergoes a predetermined address conversion and is input to the port P2. Note that the memory control circuit 13 connects a plurality of I/Os to the data bus 17.
This circuit is provided to adjust contention when 10 devices are connected. When the address signal is input to the port P2 in this way, it is sent to the I10 device port 2 through the data bus 17 and the memory control circuit 13.
can access the data.

FIG. 4 is an explanatory diagram showing the relationship between address signals supplied to the 3-port memory shown in FIG. 3 and data read out.

First, the address signals Ao-AN from the 16-bit microprocessor input to ports PO and PL have their least significant bit A' as shown in this figure. are converted into different address signals. That is, the least significant bit A'o of port PO is "1", and the least significant bit A'o of port P1 is "1".
Address signals with the same content are input to the others (A'1 to A', 4) where 'o is "0". As a result, as shown in FIG. 6(b), the upper byte data D8 to D+s of (X) are accessed from port PO, and the lower byte data D7 to D0 of (y) is accessed from port P1. It is done.

The address conversion circuit 32 shown in FIG. 3 thus operates to convert the least significant bit 80 of the address signal to A'o.

On the other hand, the address signal AoNAn from the I10 device that processes 8-bit data is directly input to port P2 as it is. That is, in this embodiment, the address translation circuit 33 shown in FIG. 3 does not substantially perform address translation operation.

In this way, as shown in Figure 4(C), 8-bit data is accessed sequentially from the highest address to the lowest address, such as (x) and (y). . In this case, this memory is used completely without waste.

FIG. 5 shows an operation explanatory diagram of another embodiment of the apparatus shown in FIG. 3.

First, address signals A0 to A from the 16-bit microprocessor input to ports PO and PL are converted into address signals that differ only in their most significant bit A'N, as shown in this figure. That is, the most significant bit A's of port PO is "1", the most significant bit A's of port P1 is "O", and the other address signals (A', -A',) have the same content. Enter. As a result, as shown in FIG. 4(b), from port PO, (X)
The upper byte data D8 to DIS are accessed, and the lower byte (y) data Dt to D are accessed from the port Pl.
0 accesses are made.

The address conversion circuit 32 shown in FIG. 3 thus converts the most significant bit 80 of the address signal to A'. It works to convert to . On the other hand, the address signal A0 to A from the I10 device that processes data with a data length of 8 bits is the least significant bit A thereof. The most significant bit A' of port P2
s is connected to port P2.

Furthermore, the other address signals A+ to AN are shifted by one bit to the lower bit side, respectively, to become A'o to A'N-.
1 to port P2. The address conversion circuit shown in FIG. 3 is, for example, a circuit in which the connections are changed in this manner.

When such a connection is made and the 8-bit data is accessed in address order as shown in Figure 5(b), the area from the highest address to the lowest address of the 3-port memory is used as the upper byte area. The upper byte area and the lower byte area are accessed alternately, such as (x) and (y). In this way, the access order can be changed depending on the method of converting the address signal input to the 3-bot memory section.

The device of the present invention is not limited to the above embodiments.

In the above embodiment, the host device has several I/Os connected to the microprocessor 11 and the memory control circuit 13.
Although the configuration is made up of 10 devices, the host devices may be connected and arranged in any other way. The configuration of the shared memory is such that the embodiment shown in FIG. 1 uses two memory elements, and the embodiment shown in FIG. 3 uses three memory elements divided into three areas.
Although an example is shown in which a port memory is used, a plurality of memory elements may be further added in addition to this, and the memory capacity and data length that can be handled may be changed in various ways. The configurations of the gate circuits of the memory selection circuit 23 and the port selection circuit 24 may be appropriately changed accordingly. In addition, an example has been shown in which the data buses of the host devices are provided separately, for example, a 16-bit data bus and an 8-bit data bus, but a part of the 16-bit data bus is shared as an 8-bit data bus. There is no problem even if the configuration is as follows.

(Effects of the Invention) In the shared storage device of the present invention described above, a storage area is appropriately selected depending on the host device used, and data of a set word length is transmitted via a data bus set for each host device. The word length and structure of the data read by the host device can be freely selected.
Furthermore, memory usage efficiency can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the shared storage device of the present invention, FIG. 2 is a block diagram of a conventional memory configuration, and FIG. 3 is a block diagram showing a second embodiment of the device of the present invention. figure,
FIGS. 4 and 5 are explanatory diagrams of the memory operation of the device of the present invention. 16a, 16b, 17-" data bus, 20... shared memory, 21a, 21b... input/output port, 22a, 22b..." switch, 23... memory selection circuit, 24... port selection circuit, 25... Address bus, 26... Control bus, 27... Bus right identification signal line, 28... Memory area selection signal, 29... Port control signal. 32.33...Address conversion circuit. Patent Applicant: Oki Electric Industry Co., Ltd. (a) 3-Bot Memory Unit Memo of the Device of the Present Invention January D7...D. Illustration by Gino

Claims (1)

[Claims] 1. A plurality of higher-level devices, a shared memory whose storage area is shared by the plurality of higher-level devices, and a memory connected to an input/output port of the shared memory and configured for each of the higher-level devices. A memory that receives a word-length data bus, a bus right identification signal that identifies which higher-level device has been granted bus rights to an address/control bus that controls reading of the shared memory, and an address/control signal. The memory selection circuit includes a selection circuit and a port selection circuit, and the memory selection circuit selects a predetermined area of the shared memory for each host device based on the bus right identification signal and the address signal. A memory area selection signal for accessing data of a set word length is output, and the port selection circuit selectively connects the input/output port of the shared memory to the data bus based on the bus right identification signal. A shared storage device characterized by: 2. A plurality of higher-level devices, a multi-port shared memory whose storage area is shared by the plurality of higher-level devices, and word-length data connected to the input/output ports of the shared memory and set for each of the higher-level devices. a bus; and an address conversion circuit provided for each of the higher-level devices, which accepts an address signal output from each of the higher-level devices and controls reading of the shared memory, and performs predetermined address conversion; The conversion circuit selectively outputs to each port of the shared memory an address signal for accessing word-length data set for each host device in a predetermined area of the shared memory. Features a shared storage device.