JPS6160163A - Data transfer system - Google Patents

Abstract

PURPOSE:To attain the transfer of data at a high speed by preparing an address at one side which concerns the transfer of data as the data output of a central processing unit and the same time using a switch means which puts said address on an address bus. CONSTITUTION:When the data on a memory part 4 is transferred to an input/ output part 5, a CPU puts the address of the data on the part 4 on a CPU address bus 9 and also puts the address of the pat 5 on a CPU data bus 8. In this case, a bus switch circuit 3 is shown in a figure (b). The address information on the bus 9 is put on a system address bus 12, and the data on the corresponding address of the pat 4 is read out and put on a system data bus 11. This data is held by a data register 6 with the data register set signal. Then the circuit 3 is changed as shown in a figure (c). Thus the address of the part 5 is put on a system address bus 12. Then the pat 5 fetches the data on the bus 11 to complete the transfer of data.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to data transfer within an information processing device,
This relates to control of transfer of data read from a storage unit and written to a peripheral device or storage unit.

[Conventional technology]

A system in which a storage unit, input/output devices, etc. are connected to an address bus and a data bus connected to a central processing unit (CPU).
Conventionally, there have been the following two control methods for outputting data stored in a storage unit to an input/output device for Wr i -te operation in a Wr i -te system.

That is, one of them is that the storage section sends data at an address specified by the central processing unit using the address bus to the data bus, passes this to a register built into the central processing unit, and then sends the data to the address bus. specifies the address of the device to which the data is to be output, and sends out the data stored in the register onto the data bus. Then, when the device with the corresponding address reads the data,
In this method, the main control for completing data transfer between the storage unit and the input/output device is performed by a program in the central processing unit.

However, the other one is Direct Memory Access (DM).
This is based on a method called A), in which a DMA control device is installed in a peripheral device, etc., and all operations other than preparation before data transfer and processing after data transfer are performed without the intervention of the central processing unit's program.
The MA control device directly transfers data between the storage unit and the input/output device, and is often used in disk devices that require high-speed table data transfer.

[Problem that the invention seeks to solve]

Of the conventional data transfer methods described above, in the former method in which the central processing unit is largely controlled by a program, data at the corresponding address sent by the storage unit onto the data bus is transferred by specifying it using an address bus. It is a two-step process in which the data is stored in a register built into the central processing unit, then the address of the destination peripheral device is specified again using an address bus, and the data is sent to the data bus. However, since there is no data transfer, high-speed data transfer cannot be expected, and the processing capacity is hindered due to the heavy burden of data transfer on the central processing unit.

In addition, in the latter method using direct memory number access, since this method is suitable for transferring large amounts of data at one time at high speed, it is difficult to use when small amounts of data are frequently transferred. There was a problem in that it could not be used to its full potential.

In view of these conventional problems, the present invention has been developed to reduce the number of problems.

The object of the present invention is to provide a high-speed data transfer method that can be used even when large amounts of data are frequently transferred.

[Means for solving problems]

According to the present invention, this object is achieved by connecting a central processing unit and a storage unit or an input/output device to an address bus and a data bus, respectively, as described in the claims.
Under the control of the central processing unit, the data sent on the data bus from the source device or area of the address specified on the address bus is transferred to the next device or area of the destination of the address specified on the address bus. In the system,
Means for switching whether to obtain the address information on the address bus from the address output or the data output of the central processing unit is provided, and the central processing unit specifies the transfer source address on the address bus, and also outputs the data in advance by the above means. A data transfer method is achieved in which data is transferred by placing a destination address prepared as a transfer destination on an address bus. In the above means, a register for temporarily holding data to be transferred is connected to the data bus, or an address bus for specifying the source address of the data and an address bus for specifying the destination address are provided separately. The purpose can also be achieved by adopting a different configuration.

[For production]

Conventionally, the central processing unit specifies the address of the υ transfer source using the address bus, stores the data sent from the transfer source onto the data bus in a built-in register, and transfers the data via the address bus in the next machine cycle. Previously, data was transferred by specifying the transfer destination address and sending the data previously stored in a register onto the data bus, but in the method of the present invention, data transfer is performed as described above. One such address is prepared as the data output of the central processing unit, and a switching means is provided to put it on the address bus, and the transfer source address and the transfer destination address are put on the address bus during the same machine cycle ( If there is one set of address buses, serially, or
If the transfer source and transfer destination have independent address buses, they can be mounted in parallel), allowing high-speed data transfer.

In the case of a method in which there is one set of address buses, the transfer source address is first placed on the data bus and data is sent to the data bus, and then the transfer destination address prepared as the data output of the central processing unit is placed on the address bus. By connecting a data register to the data bus and temporarily holding data sent by the transfer source, continuity of data on the data bus during transfer is maintained.

〔Example〕

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which 1 is a CPU, 2 is a timing control section, 3 is a bus switching circuit, 4.5 is a storage section or an input/output section, and 6 is a block diagram showing a first embodiment of the present invention.
is a data register, 7 is a CPU control bus, 8 is a CPU data bus, 9 is a CPU address bus, 10 is a system control bus, 11 is a system data bus,
12 represents the system address bus.

Figure 2 is a diagram explaining the operation of the bus switching circuit (a)
(b) shows the connection during the normal cycle, (b) shows the connection when reading data to be transferred, and (C) shows the connection when sending data to the transfer destination. Also, code 3.8.9.11
．． 12 are all the same as in FIG.

FIG. 3 is a time chart showing control in the first embodiment of the present invention. In FIG. 3, 13 represents the output signal of the timing control section (2 in FIG. 1), and the leading number 4.5 of data and address information is the storage section or input/output section 4 of FIG. It corresponds to 5. Also(
b) or (e) shows the connection of the bus switching circuit and corresponds to (b) or (c) in FIG.

The operation will be explained below with reference to FIGS. 1 to 3.゛Storage unit or input/output unit 4 (hereinafter simply referred to as storage unit 4 and °7
”) to the storage unit or the input/output unit 5 (hereinafter simply referred to as the input/output unit 5), the CPU puts the address of the data in the storage unit 4 on the CPU address bus 9, and also transfers the address of the data from the storage unit 4 to the input/output unit 5. The address of CPU is placed on the CPU data bus 8. At this time, since the bus switching circuit 3 has the connection shown in FIG.
The address information on the U address bus 9 is read, and the data at the corresponding address in the storage section 4 is read out and transferred onto the system data bus 11. This data is held in the data register 6 by the data register set signal. Next, the bus switching circuit 3 changes to the connection shown in FIG. 2(c). As a result, the address of the input/output unit 5 is placed on the system address bus 12, so that the input/output unit 5 receives the data of the system data bus 11 (data held in the data register 6), thereby inputting the data. The transfer is complete. These operations are executed in only one access cycle of the CPU, as shown in FIG.

゛ 8 ゛ Fig. 4 is a block diagram showing a second embodiment of the present invention, in which reference numerals 1, 8, and 9 are the same as in Fig. 1, 14 is an image memory, 15 is a switching circuit, and 16 is a Gate circuit, 17
18 represents a register, 18 represents an image memory address bus, and 19 represents an image memory data bus. This embodiment shows an example in which the control of the present invention is applied when data read from the image memory is written back into the image memory.

FIG. 5 is a block diagram showing a third embodiment of the present invention, in which reference numerals 1.8.9.11 are the same as in FIG.
' is a switching circuit, 16 is a gate circuit, 20 is a storage section,
Reference numeral 21 represents an input/output device, 22 an input/output address bus, and 23 a storage unit address bus. In this example,
The storage unit 20 and the input/output device 21 are connected to independent address buses, and are given address information from the CPU 1 at the same time. Since data can be read immediately, there is no need to provide a data register.

Note that in FIGS. 4 and 5, the description of the control system including the system control bus is omitted.

〔Effect of the invention〕

As explained in detail above, according to the method of the present invention, data can be transferred from the storage unit to the input/output device in one access cycle of the central processing unit in data transfer within the information processing device, so high-speed data transfer is possible. It is highly effective because it allows transfer and is applicable to cases where small amounts of data are frequently transferred.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
3 is a diagram explaining the operation of the bus switching circuit, FIG. 3 is a time chart showing the control of the first embodiment of the present invention, and FIG.
The figure is a block diagram showing a second embodiment of the invention, and FIG. 5 is a block diagram showing a third embodiment of the invention. 1... CPU, 2... Timing control section, 3... Bus switching circuit, 4, 5... Storage section or input/output section, 6... Data register,
7...CPU control bus, 8...cpU
-y-tabus, 9...CPU address bus,
lO...System control bus, 11...
System data bus, 12... System address bus, 13... Output signal of timing control section, 14... Image memo'), 15115'... Switching circuit, 16... Gate circuit, 17...
・Register, 18... Image memory address bus,
19... Image memory data bus, 20... Storage unit, 21... Input/output device, 22... Input/output address bus, 23... Storage unit address bus.

Claims (3)

[Claims] (1) A central processing unit and a storage unit or an input/output device are connected to an address bus and a data bus, respectively, and the address specified by the address bus is transferred from the source device or area to the data bus under the control of the central processing unit. In a system that transfers data sent to the address bus to the destination device or area specified by the address bus, whether the address information on the address bus is obtained from the address output or data output of the central processing unit. The central processing unit specifies a transfer source address on the address bus, and the data transfer is performed by placing a transfer destination address prepared in advance as data output on the address bus by the above means. Data transfer method. (2) The data transfer method according to claim 1, wherein a register for temporarily holding data to be transferred is connected to the data bus. (3) The data transfer method according to claim 1, wherein the address bus has a configuration in which an address bus for specifying a transfer source address and an address bus for specifying a transfer destination address are provided separately.