JPH01114961A - Directory memory access controller - Google Patents

Abstract

PURPOSE:To easily speed up a processing such as the extraction of only a specific field in a record and the extraction of a specific dimension in a multi- dimensional array by allowing the updated value of an address counter to correspond to structured data. CONSTITUTION:In case of extracting a certain field, a reading address is stored in a counter 1, and during the period of access to the field, '1' is added to the contents of the counter 1 synchronously with a data reading signal. The length of the field is previously stored in a register 7 and set up in a counter 8 before accessing respective fields. A value '1' is subtracted from the contents of the counter 8 synchronously with a data reading signal, and when the contents of the register 8 reaches zero, a 1st output signal is outputted and the length of the field is inputted from the register 7. On the other hand, a distance between records is set up in a register 2 and the value is added to the output of the counter 1 by an adder 3 and the added value is outputted as the set data of the counter 1. The data are set up in the counter synchronous ly with a 1st end signal. Thus, the succeeding objective field can be made access.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a direct memory access (hereinafter referred to as DMA) control device for transferring data at high speed in an information processing device such as a minicomputer or a microcomputer. , especially DMA for high-speed transfer of structured data.
Regarding a control device.

[Conventional technology]

CPUs can be programmed to perform general-purpose processing and can also transfer data, but the hardware is not particularly suited to data transfer, so in order to transfer data at higher speeds, a specially designed DMA control device is required. is used.

FIG. 3 shows an information processing device using such an MA control device. In this, a main memory 31, a CPU 32, and a DMA control device 33 are connected by a data bus line, an address bus line, and a data read/write signal line. FIG. 4 shows the state of the signals on these lines.

FIG. 2 shows a conventional DMA control device. This moves data from one area of the main memory to another area as follows.

That is, the addresses storing the data to be read are set in the two first counters, the addresses to be written are set in the second counter 27, and the number of data transfers is set in the third counter 23. Therefore, when the CPU inputs a DMAREQ command requesting DMA data transfer, the flip-flop 21
is set and outputs the HOLDREQ signal requesting the bus line. In response, when the CPU outputs a HOLDACK signal, the signal generator 26 starts operating due to the output of the gate 22 which takes these ANDs, and the DMA data transfer state is established.

First, the output of the first counter 29 is selected by the multiplexer 28 and output to the address bus.

Then, a data read signal is output and read out onto the data bus from that address. This data is taken into the data register 25 in synchronization with the read signal. At the same time, the contents of the first counter 29 are incremented by 1 to become the next read address.

When the data is loaded into the data register 25, the multiplexer 28 selects the output of the second counter 27 and outputs it to the address bus. Output buffer 2 activated at this time
4, the data taken into the data register 25 is output onto the data bus. Then, a data write signal is output, and data is written to the address specified by the output of the second counter 27. At this time, the contents of the second counter 27 are incremented by 1 so as to become the next write address.
The contents of the third counter 23 are incremented by -1.

If the content of the third counter 23 is not zero, the data transfer is repeated. If this becomes zero, the flip-flop 21 is reset and the DMA data transfer state ends.

The signal generator 26 outputs data read and data write signals to the outside, and also outputs data read and write signals to the outside, and also outputs data read and write signals to the outside, and also outputs data read and write signals to the outside.
23, a switching signal for the multiplexer 28, a strobe signal for the data register 25, an activation signal for the data buffer 24, etc.

[Problem that the invention seeks to solve]

Processing structured data that is often handled by information processing equipment When extracting and processing only a specific field in record format data, or extracting and processing only data in a specific dimension in multidimensional array data In case,
Conventional DMA control devices have a problem in that they cannot handle this problem because they can only transfer data with consecutive addresses.

[Means for solving problems]

The DMA control device of the present invention includes a first counter in which first setting data is set in synchronization with a first end signal and changes by the number of units in synchronization with a second signal, a first register, and the first counter. a first adder that adds the value of the first register to the output value of the device and outputs first setting data; and second setting data that is set in synchronization with the first end signal and is set in synchronization with the second signal. a second counter that changes by the number of units, a second register, and a second counter that adds the value of the second register to the output value of the second counter;
a second adder that outputs setting data; a third register;
a third counter that counts the second signal and when the set value of the third register is finished, generates the first end signal and returns to the initial state; and a third counter that counts the first end signal and counts the specified value. a fourth counter that generates the second termination signal when completed;
It has an MA processing function, uses the output of the first counter as a read address, uses the output of the second counter as a write address, outputs the second signal and data read and data write signals synchronized therewith, and outputs the second end signal. When is output, DMA
It is comprised of a control circuit that ends a data transfer operation, and a fourth register that takes in data in synchronization with the data read signal and outputs this data in synchronization with the data write signal.

[Effect]

In the DMA control device of the present invention, since the update value of the address counter corresponds to structured data, a specific portion of such data can be extracted at high speed.

〔Example〕

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a DMA control device according to the present invention. In this figure, 1 is the first counter, 2 is the second register, 3 is the first adder, 4 is the second counter, 5 is the second register, 6 is the second adder, 7 is the fourth register, 8 is a third counter, 9 is a fourth counter, 10 is a control circuit, and 11 is a data register.

When extracting a certain field from a plurality of records, the read address is stored in the first counter 1, and is incremented by 1 in synchronization with the data read signal while the field is accessed. The length of the field is stored in the fourth register 7 and is set in the third counter 8 before each field is accessed.

The third counter 8 is decremented by 1 in synchronization with the data read signal, and when it becomes zero, it outputs the first output signal and takes in the field length from the fourth register 7. The distance between records is set in the second register 2, and the first adder 3 adds this to the output of the first counter 1 and outputs it as setting data for the first counter 1.

This data is set in the first counter 1 in synchronization with the first end signal. In this way, the target field of the next record can be accessed.

The write address is the output of the second counter 4, and similarly to generating the read address, the second register 5 and second adder 6 can be used to write data to another structured record.

The number of fields to be transferred is set in the fourth counter 9, and when it is subtracted by 1 and becomes zero by the first end signal output from the third counter 8, the second end signal is set to the fourth count. The signal is output from the device 9, and the DMA data transfer state ends.

The control circuit 10 outputs a HOLDREQ signal to the CPU in response to a DMAREQ command input from the CPU, and outputs a HOLDREQ signal to the CPU.
When the CK signal returns, DMA data transfer is started.

Here, the control circuit 10 outputs the output of the first counter 1 to the address bus, and outputs a data read signal (read). The data read onto the data bus is set in the data register 11.Next, the control circuit 10 sends the data to the second counter 4.
output to the address bus and output a data write signal (write). At the same time, the data register 11 outputs the set data to the data bus. This completes one data transfer, and as mentioned earlier, each counter 1°4.8
．． 9 is updated, and MA data transfer is performed by extracting only a specific data field from a plurality of records.

Note that although the counter in the above explanation updates by +1, the same effect can be obtained by giving the distance between records as a negative number even if the counter updates by -1. It does not limit the scope of the claims.

〔Effect of the invention〕

According to the present invention, it is possible to easily speed up the processing of structured data, that is, the processing of extracting only a specific field of a record or extracting a specific dimension of a multidimensional array.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of a conventional example, Fig. 3 is a diagram of an example of application of the system of Fig. 2, and Fig. 4 is a block diagram of each signal of the system of Fig. 3. This is a diagram. 1.4, 8.9, 23, 27.29... Counter, 2.
5.7...Register, 11.25...Data register, 3.6...Adder, 10...Control circuit, 21.
...Flip-flop, 24...Buffer, 26...
- Signal generator, 28...Multiplexer, 31...
Main memory, 32... CPU, 33... DMA control device.

Claims (1)

[Claims] The first setting data is set in synchronization with the first end signal, and the second
a first counter that changes by the number of units in synchronization with the signal;
a register, a first adder that adds the value of the first register to the output value of the first counter and outputs first setting data; and second setting data that is set in synchronization with the first end signal. a second counter that changes by the number of units in synchronization with the second signal; a second register;
a second adder that adds the value of the register and outputs second setting data; a third register; and a third register that counts the second signal and generates the first end signal when the set value of the third register is finished counting. a third counter that returns to the initial state; a fourth counter that counts the first end signal and generates the second end signal after counting the specified value;
The output of the counter is used as a read address, the output of the second counter is used as a write address, and the second signal and data read and write signals synchronized therewith are output, and when the second end signal is output, DMA data transfer is performed. A direct memory access comprising a control circuit for terminating an operation, and a fourth register for capturing data in synchronization with the data read signal and outputting the data in synchronization with the data write signal. Control device.