JPS59136830A - Direct memory access controller - Google Patents

Abstract

PURPOSE:To realize a function to transfer continuously data blocks by providing a circuit to which the head address of each of plural memory blocks are set and a circuit to which the number of data transferred within each block is set. CONSTITUTION:The head address of a data block group to be used as a source is set at a source address register 11; while the head address of a memory region to be used as a destination is set at a destination address register 12. At the same time, the number of data within the data block is set at a base counting register 31 and a counting register 13 respectively. The number of transferred blocks is set at a block counting register 32, and the fixed address displacement between data blocks is set at a displacement register 33. An adder 34 which generates an address during a direct memory access operation functions as an incrementer during transfer of data and then as an adder when the head address of the next data block is delivered from an optional data block.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a direct memory access (hereinafter referred to as DMA) control device that performs data transfer between memories without going through a central processing unit (hereinafter referred to as CPU). .

When transferring a large amount of block data in a memory area to another area using a general KCPUi, the CPU controls reading and writing to the memory, so the transfer speed is significantly increased due to the CPU's instruction food fetch operation. This is avoided by adopting an MA control device (ftr)r. For example, in image processing, etc., is the number of data the same? Generally, a plurality of data blocks arranged at equally spaced addresses are transferred to another area. This is the case when a part of the screen is reorganized into another area as a rectangular window.

Figure 1 (altj: represents the image on the screen. There are n pieces of data (X11 + X12
+...

Data block 1 has n data (X21 + X22 +..., X2fl), data block 2 has n data (X31 *X32
+ , . . . x3n) Data block 3 with e,
n pieces of data (X41.X42°..., X4r+)e
Data block 4 has data block 2, starting data x21 of data block 2, and starting data x31 of data plotting 3.
and the address of the first data X41 of data block 4 are the address of the last data X1n of data block 1, the last data X2n of data block 2*the last data X3n of data block 3, plus L+mf.

FIG. 1 (bl is a memory map corresponding to the image on the screen of (al), data block 5 is attached to cheater block 1, data block 6 is attached to data block 2, data block 7 is attached to data block 3, data block 8 is attached to correspond to the data block 4. The cheater blocks 5 to 8 each have the same number of data on the memory and are arranged in the memory space at regular intervals. The memory map is shown when data blocks 5 to 8 are successively rearranged.
A conventional example of transferring a data block group to the memory arrangement shown in FIG. 1 (cl) will be explained below. FIG.
In the block diagram of the MA control device, the part surrounded by the 0-dot line is the IJMA control device tlO. Prior to transferring one data block, the start address of the data block to be the source is entered into the source address register 11, the start address of the destination memory area is entered into the destination register 12, and the number of data in the data block to be transferred is entered. It is necessary for the CPU to set each of the count registers 13. When the DMA transfer process starts here, the bus control circuit 14 outputs a bus hold request signal 15 to the CPU, and when a bus hold response signal 16 is returned in response, the memory is accessed. start. Initially, the address set in the address register 11 is output from the address output port 17 to the external address bus, and at the same time, the memory control circuit 1B outputs the memory read signal 19, and the data at the specified address is transferred to the external address bus. The data is stored in the tempo tree register 20 through the data bus. Next, the address set in the nice next address register 12 is outputted from the address output port 17 to an external address bus. After that, the data stored in the tempo 2 reregister 20 is output to the external data bus, and at the same time, the memory control circuit 18 outputs the memory write signal 21 to write the contents of the temporary register 20 to the specified address. It will be. During this series of bus cycles, the contents of the source address register 11 and the contents of the destination address register 12 are increased or decreased by the incrementer/decrementer 22 to generate address information for the next data transfer. Further, the contents of the count register 13 are updated by the decrement/removal 23, and a comparison is also made to see if the value has become 0. Therefore, when DMA ends, the value set in count register 13 is O.
At this time, one data block has been transferred. When the DMA ends, the bus hold request signal is no longer output and the use of the 9 bus is transferred to the CPU. Therefore, when reorganizing a data block group using a conventional DMA control device, it is necessary to set the start address information regarding the memory of the MA control device once per transfer of one data block. There was overhead time for the CPU to perform the data transfer. When the number of data blocks is small, the ratio of CPU overhead to the transfer time of all data block groups is small, but when the data area to be handled is large, such as in image processing, the number of data blocks is inevitably large. turn into. In such cases, the conventional transfer method using a DMA control device has the disadvantage that the transfer speed is reduced by the overhead caused by the CPU.

An object of the present invention is to provide a DMA control device k that has a function of continuously transferring data blocks without the intervention of a plurality of data blocks IcPU.

The present invention has a circuit in which the start address of each of a plurality of memory blocks to be transferred is set, and a circuit in which the number of randoms to be transferred in each block is set. This patented transfer device is characterized in that the data transfer t-cPUi within the block is executed continuously without using the start address bus of another block.

When the present invention is used in a DMA device for image processing and the number of data in each data block is the same and each block is arranged at equal address intervals, the following configuration is suitable.

That is, at least a means for storing the start address of a data block group, a means for storing the start address of a storage area in which transfer data is stored, a means for storing the number of transfer data in the data block, and a means for storing the number of transfer data in the data block. means for storing the address displacement between the blocks; means for storing the number of data blocks in the data block group; and means for storing the number of data blocks in the data block group; means for generating an address; and means for decrementing the number of transferred data by the number of cheater blocks written in mJ; When the number of data to be transferred becomes 0, the spinning address generating means generates all starting addresses of the next data block, thereby performing direct memory access control such that data transfer between the data block group and the storage area is performed continuously. It is a device.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram of a DMA control device according to an embodiment of the present invention. The part surrounded by the dotted line is the DMA control device 30. Memory, inter-memory cheetah block group DM
When performing all A transfers, the start address of the data block group that becomes the source is stored in the source address register 11, and the destination -7! The start address of the memory area to be used as the destination is set in the destination address register 12, respectively. Further, the number of data in the data block to be transferred is constant, and its value is set in the base count register 31 and the count register 13. The steps up to this point are the same as when using the conventional DMA control device fIIL, in addition to this, the number of blocks to be transferred is set in the total block count register 32, and a constant address displacement between each cheater block is set in the displacement register 33. do. The adder 34, which generates an address during DMA operation, works as an incrementer when transferring data within each data block, and works as an adder when outputting the start address of the next data block from an arbitrary data block.

Here, the actual DMA operation will be explained in detail using the memory maps of (b) and (cl) in Figure 1.The address set in the source address register 11 is output to the address bus, and Xll is accessed and temporarily stored in the temporary register 2o.

Next, the address set in the destination address register 12 is output, and Xll stored in the temporary register 2o is written to that address. In the next data transfer, the address set in the source address register 11 is incremented by the adder 34, and X12 in BL is accessed and temporarily stored in the tempo 2 register 2°. The address set in the address register 12 is incremented by the adder 34, and X12 stored in the temporary register 20 is written to that address.This operation is repeated until the transfer is performed as shown in FIG. When X l n vrk is sent, the count register 13 becomes zero and the contents of the best count register 31 are reset. At the same time, the contents of the block count register 32 are decremented by 1 by the decrementer 23. .Furthermore, the start address of the data block to be transferred next is not the address of Xln incremented, but the address displacement between blocks set in the displacement register 33 is added by the adder 34. The address between these blocks The address generated by adding the displacement is output to the address bus and
X21 in FIG. The data block group that is displayed is relocated to the area shown in FIG. 1 (clK).

As described above, this embodiment eliminates the need for resetting address information by the CPU for each data block transfer by simply adding a small amount of hardware to the conventional DMA control device in DMA transfer of a data block group. It becomes possible to access all the data 21022 groups continuously. Therefore, it is possible to improve bus usage efficiency and perform data transfer at high speed. This effect becomes more pronounced as the number of data blocks increases.

In this embodiment, the data block group is considered as the source side, but the DMA is considered as the destination side.
It is also possible to do this. Furthermore, the start address of the next data block was generated by adding the address displacement between blocks, but if the address within the block is decremented and generated, a similar effect can be achieved by using a subtracter instead of an adder. is obtained. Of course, if the number of doors within a block or the address displacement between blocks is different,
It would be a good idea to provide a corresponding set circuit.

[Brief explanation of the drawing]

In Figure 1, (at is the data layout diagram on the screen, and (b) is (
FIG. 3 is a memory map diagram corresponding to al. (cl
is a memory map diagram that becomes a destination area during data transfer. Figure 2 shows a conventional DMA control device.
This is a zero diagram. FIG. 3 is a DM showing an embodiment of the present invention.
It is a block diagram of A control device. 1.2, 3, 4, 5, 6, 7.8... data block, 10... DMA control device, 11...
- Source address register, 12... Destination register, 13... Count register, 14... Bus control circuit % 15...
...Bus hold request signal, 16...Bus hold request response signal, 17...Address output port, 18...Memo control circuit, 19...
・Memory read signal % 20...Temporary register, 21...Memory write signal, 22...
... Incrementer, 30 ... DMA control device, 31 ... Base count register, 32
...Block count register, 33...
...Displacement register, 34... Machining trace (a) No. (F) (C)
1 figure

Claims (1)

[Claims] It has means for storing the start addresses of each of a plurality of memory blocks, and means for storing several pieces of data to be transferred in the memory block, and after the data transfer in one memory block is completed, it is possible to transfer data to other memory blocks. Data transfer within the memory lock using the first address key f CPIJ' (
A direct memory access control device characterized by continuous execution without intervention.