JPS62108341A - Memory data transferring system - Google Patents

Abstract

PURPOSE:To execute data transfer at a high speed by constituting the titled system so that data transfer between different memory blocks can be executed in one cycle. CONSTITUTION:When executing data transfer, in case when its transfer origin and transfer destination exist in different memory blocks, a '0' signal is applied to an adder/subtracter 61 by outputting an address command 1 from a CPU, and an even address for a memory block 11 of the transfer destination is set to an offset '0'. On the other hand, a difference in addresses between the transfer origin and the transfer destination of data is set in advance to an offset register 5. As a result, prescribed even address and odd address are given to the memory blocks 11, 12, respectively, from each adder/subtracter 61, 62. In this state, when the CPU reads out data from the transfer origin memory block 11, and the data is loaded on a bus 2 so as to be written on the transfer destination memory block 12, the data transfer between both the memory blocks 11, 12 can be ended in one cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory data transfer method for transferring data between memories.

Traditionally, when data is transferred between memories connected to one data bus, it takes two cycles (read and write cycles) for each piece of data via the CPU's registers. The data transfer is performed between the two devices, and the data transfer takes time.

The present invention has been made in consideration of the above points, and provides a memory data transfer method that allows data transfer between memories to be performed at high speed.

In order to achieve the objective, the present invention divides the memory into multiple blocks, and when data is transferred between different memory blocks, each memory block is supplied with a different address, and the data in one memory block is Read data from one memory block and write data from the other memory block simultaneously, and transfer data between each memory block using a common data bus.
This is done in cycles.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the memory data transfer method according to the present invention, by dividing the memory into a plurality of blocks and providing each memory block with an independent address bus, when data is transferred, the source and destination are not the same memory block. Only in certain cases, data reading and data writing from each memory block are performed simultaneously.

FIG. 1 shows an embodiment of the present invention in which the memory is divided into two blocks 11 and 12, each of which is connected to a common data bus 2 in a CPU (not shown). Also, each memory block 1
1.12 address buses, even address bus 31.1 for memory block 11; Odd address buses 32 for the memory blocks 12 are provided independently, and the values obtained by adding and subtracting the register values in the offset register 5 and the specified address values from the external address bus 4 connected to the CPU by adders/subtractors IL and 62 are calculated as even numbers. The address can be specified as an odd number address. Also, the address command LL O74 is sent from the CPU.
When the address command II II I+ is issued from the CPU, the adder/subtractor 62 is selected, and the adder/subtractor 61 is selected via the inverter when the address command II II I+ is issued from the CPU.

If the transfer source and transfer destination are in different memory blocks when currently transferring data 1 For example, memory block 11
When data is to be transferred from the memory block 12 to the memory block 12, the CPC outputs the address command 111 Hl and gives the adder/subtractor 61 a ``'0'' signal, thereby setting the even address for the transfer source memory block 11 at an offset O. On the other hand, the difference between the addresses of the data transfer source and data transfer destination is set in the offset register 5 in advance.

However, if this is done, predetermined even and odd addresses will be given to the memory blocks 11 and 12 from each adder/subtractor 61 and 62, respectively. When the CPU reads data from the transfer source memory block 11 in such a state, the read data is transferred onto the data bus 2, so that the read data is transferred to the transfer destination. By writing to the memory block 12, data transfer between the memory blocks 11 and 12 can be completed in one cycle.

By incrementing the address one after another in this state, data transfer in a certain memory area becomes possible.

FIG. 2 shows the timing of data transfer at that time. In the figure, M indicates an even numbered address of the transfer source, and N indicates an odd numbered address of the transfer destination.

In addition, when transferring data, if the transfer source and transfer destination are the same memory block, as in the past, the data is transferred via the CPU register in two cycles: a read cycle and a write cycle. will be carried out.

EFFECTS - 1 or more In the memory data transfer method according to the present invention,
It has the excellent advantage that data transfer between different memory blocks can be performed in one cycle, and the data transfer can be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a system configuration for concretely implementing the memory data transfer method according to the present invention, and FIG.
The figure is a time chart showing the timing of each part signal when the present invention is implemented in the same system configuration. 11.12...Memory block 2...Data bus 31...Even address bus 32...Odd address bus 4...External address bus 5...Offset register 61.62...Adder/subtractor No. Figure 1 Figure 2 U4 To (beg! / ”

Claims (1)

[Claims] When dividing memory into multiple blocks and transferring data between different memory blocks, each memory block is supplied with a different address,
Memory data transfer in which reading data in one memory block and writing data in the other memory block are executed simultaneously, and data transfer between each memory block is performed in one cycle using a common data bus. method.