JPS5837633B2 - Buffer memory storage control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a buffer memory storage control system, particularly in a data processing device in which information in units of one block is divided into M times and transferred to the buffer memory when a block is loaded. N transfer information given by ≦M is written into the buffer memory at one time, thereby shortening the time when the buffer memory is unavailable for the above-mentioned block loading, and reducing the buffer memory. The present invention relates to a buffer memory storage control method that correctly separates the load destination into memory.

In a data processing device having a buffer memory, the average processing execution time T is the average processing time on the buffer memory TBF, the average access time to the main memory device TACC, and the buffer memory not found. When NF is the ratio at which , occurs, it is given by .

From this, it can be seen that the smaller the ratio NF is, the more the average execution time T
becomes small.

One way to reduce the ratio NF is to increase the capacity of the buffer memory itself so as to limit the amount of information transferred from the main memory.

Although this measure is effective, it results in an increase in high-speed memory capacity, which significantly increases costs.

Another measure is to take the size of one block stored on the buffer memory into account and to reduce the ratio NF considering that addresses are generally incremented.

However, in this case, once a block load is required, the problem is that the number of data transfers increases if the bus width with the main storage device is fixed.

That is, if the size of one block unit is doubled, the number of transfers will be doubled if the bus width remains unchanged, and the possibility that the buffer memory will be busy during that time increases.

The present invention aims to solve the above-mentioned problems, and also aims to correctly separate the load destination.The buffer memory storage control method of the present invention allows the size of one block to be L× It is equipped with a buffer memory of M bytes and a main storage device with a transfer bus width of L bytes, and has N write registers of L bytes wide (N≧2) for the data section of the buffer memory, and stores LXN bytes of information at once. In the buffer memory to be written to the data section, the main storage device stores M at the time of block loading.
The transfer order for the buffer register side is controlled so that the information transferred in batches is not transferred to the same register among the N write registers within one write synchronization for the data section. and the write register holds transfer order information in units of L bytes, and uses this as address information when writing to the data section of the buffer memory divided into N sections. It is characterized in that it is structured so that it can be written in units of arbitrary L bytes.

This will be explained below with reference to the drawings. FIG. 1 is an explanatory diagram for explaining the conventional problems, FIGS. 2 and 3 are explanatory diagrams for explaining the concept of the present invention, FIG. 4 is an embodiment of the configuration of the present invention, and FIG. 5 is an explanatory diagram for explaining the concept of the present invention. An example is shown in which the main parts are enlarged.

As mentioned at the beginning of this specification, in a data processing device having a buffer memory, when the buffer memory is not found, one block of information containing the desired information is loaded onto the buffer memory. be made to do.

Now, if the size of one block is 64 bytes and the bus width between it and the main storage device is 8 bytes, the data will be loaded from the main storage device eight times.

That is, as shown in FIG. 1, one block of information 1 stored in the data section of the buffer memory is loaded from the main storage device to the data register 2 in units of 8 bytes.

Then, the data portion of the buffer memory will be written eight times.

For this reason, assuming that Tw is the time required for one write, the buffer memory is in a busy state for a time of 8 Tw during block loading.

For this reason, in the present invention, as shown in FIG.
The information transferred in batches is compiled and then written on the buffer memory.

In FIG. 2, 1-0 indicates even-numbered byte side information of one block of information stored on the buffer memory, 1-1
is also odd number side information, 210 is even number side information data register, 2-1 is odd number side information data register, 3
-0 represents an even number by 1 side information write register, and 3-1 represents an odd number byte side information write register.

As shown in the time chart in FIG. 3, when a block is loaded, for example, even number side information E and odd number side information (or odd number side information and even number side information) are loaded from the main storage device MCU. When the even number side information is #O
Set data register 2-0 and odd number side information #
1 data register 2-1, and then both are simultaneously transferred to write registers 3-0 and 3-1 for writing.

The situation during this time is shown in FIG.

In other words, as shown in the figure, when even number side information E, odd number side information O, even number side information E, etc. are transferred, both pieces of information are written at the timing when odd number side information O is transferred. Register 3-0. 3-1 to perform writing as shown in the figure.

As a result, the write time caused by one flock load is 4TW, compared to the case shown in FIG.
The possibility of being busy is reduced.

In the case of the block load described above, the transfer is generally performed in eight steps, and the byte information that is needed for the time being is transferred first.

Therefore, if the first byte information to be transferred is odd number side information O, it will be transferred in the order of 0, E, 0, . . . .

However, even in this case, the even number side information is stored in register 2-0.
Further, the odd number side information is set in the register 2-1, respectively.

In order to do this, it is sufficient to allocate the bytes according to the content of the least significant bit of the byte information and instruction address information transferred from the main memory side.

Furthermore, when writing to the buffer memory from an arithmetic processing unit (E-UNIT) not shown, the write data is directly transferred to the write register 3-0. Just set it to 3-1.

FIG. 4 shows the configuration of an embodiment of the present invention, and the reference numeral 3-
0, 3-1 correspond to FIG. 2, 4 is the effective address register, 5 is the main memory access address register, 6 is the tag part of the buffer register, 7 is the data part of the buffer register, 8 -0 to 8-F are a total of 16 associative units in the tag part, 9-00, 9-01, 9-10
and 9-11,...9-FO and 9-F1 are a total of 16 associative units in the data section, 10-0 to 101F are comparators, respectively, and 11-0 to 11-F. 12 represent selection circuits, and 12 represents an address bit holding section.

In the case shown in the figure, the one-block corresponding area (hatched area in the figure) that stores one block's worth of information in the data section 7 is divided into two areas of 8 bytes each.

Address information regarding the contents of the 1-block corresponding section constituted by the two areas is stored in the hatched area in the tag section 6.

When effective address information EAR is set in register 4 upon access from an arithmetic processing section (not shown), tag section 6 and data section 7 are respectively accessed by bits 20 to 25 in the illustrated case.

At this time, as is well known, one of the 64 pieces of address information stored in each of the associative units 8-0 to 8-F of the tag section 6 is selected and the comparators 10-0 to 10-F
-F is read.

It is then compared with bits 8 through 19 in register 4.

If comparator 10-1 issues a matching output, then
At this time, the associative units 9-10, 9-1 in the data section 7
The data read from 1 matches the data currently accessed and is passed through the selection circuit 11-1 to the arithmetic processing unit E.
- Passed to IJNIT (of course, it is divided into bytes by a configuration not shown; for example, 1 byte of information).

In the above access, the comparators 10-0 to 10-F
If none of them produce a matching output, it is assumed that the desired information does not exist in the buffer memory, and the buffer memory is
Memory Not Found.

Then, a block load is performed to the main memory side device according to the contents of the main memory access address register 5.

At the time of loading the block, processing as described with reference to FIGS. 2 and 3 is performed.

The description will be continued below with reference to the enlarged view of the main parts shown in FIG.

In FIG. 5, the symbols 1-0, 1-1, 210, 2-
1, 10, 3-1 correspond to Figure 2 or Figure 4,
1 2-0 and 1 2-1 are the addresses shown in Figure 4.
It corresponds to the bit holding section 12.

Further, 13-0, 13-1 are selection circuits, 14-0, 1, respectively.
Reference numeral 4-1 represents a byte instruction address information holding unit provided from the main storage device.

As explained in connection with FIG. 3, when a block is loaded, the byte information required for the time being is first transferred from the main storage device.

Therefore, it is undetermined whether the byte information is the above-mentioned even number side information E or odd number side information O.

For this purpose, as shown as bit information in the main memory access address register 5 shown in FIG. Try to give.

As a result, the main memory side device can specify the byte information that is needed for the time being, and if bit 28 of the address information bits of the byte information is logic "0", it is even number side information E. , if the logic is "1", it is determined that the odd number side information is O.

Then, if the byte information is even number side information E,
It is set in the illustrated register 2-0.

At this time, when transferring the byte information, the main storage side device transfers the byte information byte instruction address information bit (
Bits 26, 27, 28) are transferred together, bit 28 is controlled to be set in register 2-0, and bits 26 and 27 are set in byte instruction address information holding unit 14-0. controlled to do so.

Below, the main storage side device stores byte information O, E, 0...
They are transferred alternately like...

In this case, as explained with reference to FIG. 3, the contents of register 2-0 and register 2-1 are
The contents of are set in write registers 3-0 and 3-1, respectively.

On the other hand, a unit that stores even number byte side information 1-0 according to the contents of the byte instruction address information holding section 14-00}
A write access is made to the 9-*0 side, and the odd-numbered byte side information 1-1 is also written according to the contents of the holding section 14-1.
A write access is made to the unit }9-*1 storing the unit.

Note that during this write access, although it is not clear in FIG. 5, the effective address and
Access address information is also given to the data portion T by bits 20 to 25 from the contents of register 4.

For this purpose, one block corresponding portion (for example, the shaded area in FIG. 4) is accessed by the bits 20 to 25, and the bits 26 and 27 access the block corresponding portion, respectively.

Even if the byte information is transferred as E, 0, E, 0, etc. as described above, the odd number side information O that is transferred second will be any of the four byte information shown in the diagram. It may be.

Which of these is determined depends on the availability of banks in the main storage device and is random.

The bits 26 and 27 indicate which one of them is, and thereby ensure that writing is performed at the correct location.

As explained above, according to the present invention, the frequency that the buffer memory becomes busy can be reduced, and the size of the block unit can be increased without increasing the busy state, resulting in buffer memory not found. You can reduce the frequency.

By adding the SEL circuit 15 in FIG. 5, the transferred data that has not been written to the buffer memory can be bypassed and sent to the arithmetic unit.

Furthermore, in the description of the above embodiment, it has been shown that the value L in the present application is 8 bytes, the value M is 8, and the value N is 2, but the present invention is not limited thereto.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining the conventional problems, FIGS. 2 and 3 are explanatory diagrams for explaining the concept of the present invention, FIG. 4 is an embodiment of the configuration of the present invention, and FIG. 5 is an explanatory diagram for explaining the concept of the present invention. An example is shown in which the main parts are enlarged. In the figure, 1-.0 is even-numbered byte side information, 1-1 is odd-numbered byte side information, 2-0 is even-numbered byte side information register, 2-1
is the odd-numbered byte side information register, 310 is the even-numbered byte side information write register, 3-1 is the odd-numbered byte side information write register, 4 is the effective address register, 5 is the main memory access address register, 6 is the tag 7 is a data section, 10 is a comparator, 11 is a selection circuit, 12 is an address/bit holding section, 13 is a selection circuit, 14 is a byte/finger 1
This represents an address information holding unit.

Claims (1)

[Claims] 1. A buffer memory with a block size of LXM bytes and a main storage device with a transfer bus width of L bytes are provided, and N write registers each having a width of L bytes (N≧2) are provided for the data section of the buffer memory; LXN
In a buffer memory that collectively writes bytes of information to the data section, the main storage device transfers the information transferred M times during a block load to the data section within one write synchronization period. The write register is configured to control the transfer order to the buffer register so as not to be transferred to the same register among the write registers, and the write register holds transfer order information in units of L bytes and is divided into N pieces. The present invention is characterized in that the data section of the buffer memory divided into N pieces can be written in units of arbitrary L bytes by using address information when writing to the data section of the buffer memory. Buffer memory storage control method.