JPS6121543A - Data transfer device - Google Patents

Abstract

PURPOSE:To improve remarkably transfer efficiency by dividing the address of a memory into odd-and even-number banks and transmitting data from a data bus to both the banks at the same time. CONSTITUTION:An address switch 9 is changed over to the position of the hard disc 11 by a command from a CPU7 and outputs a DMA command to a DMA controller 8. For example, the data from the hard disc device 11 according to the said command, for example, is written on the 1st memory 12. When an address data from the DMA controller 8 is an odd number in this case, a data is written on the 1st memory 12 and when an address data is an even number, the data is written on the 2nd data. When the transfer is finished, both the 1st memory 12 and the 2nd memory 13 are changed over to the position of the data bus 14. The 1st memory 12 and the 2nd memory 13 are accessed at the same time in the access from the data bus 14 and the even- and odd-numbers are transmitted at the same time and the transfer efficiency at the data bus position is doubled.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data transfer device used in a storage device of a computer or the like.

1. Configuration of a conventional example and its problems FIG. 1 shows a configuration diagram of a conventional data transfer device. Second
The timing chart is shown in the figure.

In response to an instruction from the central processing unit (hereinafter abbreviated as CPυ) 1, the address switch 2 switches to the node disk 3 side and issues a DMA instruction to the direct memory access (hereinafter abbreviated as DMA) controller 4. . For example, when reading from the hard disk 3, follow these instructions and
- The contents from the hard disk 3 are written to the storage element 6 in 8-bit units. When the writing is completed, the completion information is sent from the DMA controller 1 to the CPU 1 by 3Av and CPt.
Jl switches the address switch 2 to the system side, and the contents of the memory 6 are transferred to other memories etc. in 8-bit units via the data bus 6.

However, when data is transferred with a 1:1 correspondence between the memory on the system side and the node disk side, 8
Because only bit data can be transferred, the system's transfer efficiency decreases.

OBJECTS OF THE INVENTION It is an object of the present invention to eliminate these conventional time losses and realize highly efficient data transfer.

Structure of the Invention The present invention improves the efficiency of the system by dividing the memory into odd and even banks based on addresses, and transferring these by 16 bits on the system side.

DESCRIPTION OF EMBODIMENTS 7 is a CPU, to which control signal lines are connected to send control signals to a DMA controller 8, an address switch 9, and a data switch 10. Further, the DMA controller 8 and the address switch 9 are connected by an address data line,
Address data is sent from the DMA controller 8 to the seat address switch 9. Further, the DMA controller 8 and the hard disk device 11 are connected by an address data line.

The address switch 9 is configured so that the address switch 9 sends odd and even address data to a first storage element (hereinafter abbreviated as memory) 12 and a second memory 13, respectively.
Odd and even address data lines are connected to the first and second memories 12 and 13, respectively.

The data switch 1o has a hard disk device 11, a first memo, and a second memo! A data line is connected to J12 and J13 so that data can be sent and received, and a data line is further connected to a data bus 14.

The address bus 16 is connected to the address switch 9 and address data lines.

Next, the operation will be explained. First, in response to an instruction from the CPU 7, the address switch 9 switches to the hard disk device 11 side and issues a DMA instruction to the D, MA controller 8. For example, when reading data from the hard disk device 11, the data from the hard disk device 11 is written to the first memory 12 according to this instruction. At this time, if the address data from the DMA controller 8 is an odd number, the data is written to the first memory 12, and if the address data is an even number, the data is written to the second memory 13. When the transfer is completed, the address switch 9
Both the first memory 12 and the second memory 130 are switched to the data bus 14 side.

Access from the data bus 14 side accesses the first memory 12 and the second memory 13 at the same time, and transfers odd and even numbers at the same time, doubling the transfer efficiency on the data bus side. I will do it.゛In the conventional example, T is required for DMA transfer from the hard disk device.
Assuming that it takes 1 hour and 12 hours for DMA transfer from the data bus side, a total of T1+12 hours is required.

In the present invention, the time is T, 10T2/2, and the time efficiency from the data bus side is halved. ``Also, data bus 1
The same thing can be said for the case where data is written from the 4 side to the hard disk device 11 via the memories 12 and 13. □ Effects of the Invention As described above, the present invention can greatly improve transfer efficiency by dividing the memory into odd and even banks and transmitting data from the data bus to both banks simultaneously.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional example of a data transfer device, FIG. 2 is a timing chart based on FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. It is a timing chart based on a figure. 7...Central processing unit, 8...DMA controller, 9...Address switch, 1o...Data switch, 11...Hard disk device, 12...
...first memory element, 13...second memory element,
14...data bus, 16...address bus. Name of agent: Patent attorney Toshio Nakao (1 person)
5 Figure 4

Claims (1)

[Claims] It has first and second storage elements, the addresses of the respective storage elements are odd and even numbers, the first and second storage elements are connected to the storage device via an address switch and an address controller, and the A data transfer device characterized in that first and second storage elements are connected to a data bus via a data switch.