JPS6217879Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a multiplex processing device equipped with communication means between processing systems.

[Conventional technology]

Conventionally, the following two types of methods have been used to communicate between systems in such a multiplexing processing device.

FIG. 1 is a block diagram showing the configuration of a conventional multiplexing processor. In FIG. 1, a shows a method in which both systems communicate through a common memory provided between them. In the figure, 1 is the central processing unit (CPU) of one system (system A), 2 is the memory of system A, and 3 is the bus line of system A. Also, 4 is the central processing unit (CPU) of the other system (system B), 5 is the memory of system B, and 6 is the bus line of system B. 7 is a common memory, which is connected to systems A and B via buses 3 and 6, respectively. With this configuration, both systems can read and write data into the common memory as if it were their own system's memory, thereby enabling communication between the two systems. In this case, the common memory appears as a memory from both systems, so
The advantages of this configuration are that there are fewer procedures for communication between systems, and the data transfer speed between systems is high. However, in this configuration, only the common memory section is not multiplexed but has a single configuration, which makes the reliability of the memory an issue.
Furthermore, if power is supplied to the common memory from either system, the two systems will not have the same configuration, which has the disadvantage that the device configuration and power supply configuration will become complicated.

In FIG. 1, b indicates a method in which both systems are equipped with a digital input/output circuit DIO, and both systems communicate via this. In the figure, symbols 1, 2,
The representations of 3, 4, 5, and 6 are the same as in Figure 1. 8 and 9 are A-system and B-system DIOs, respectively. In the configuration shown in FIG. 1b, both systems can access the other system in the program mode by viewing the other system as an input/output circuit (I/O). For example, when trying to send data from system A, once the data is written to DIO8 of the own system, this data is transferred to DIO9 of system B. The B system learns that the data has been written by the interrupt, and
By reading the data of DIO9, it is possible to receive communication from the A system. In this case A
Since the system and B system have the same configuration, there is an advantage that each system can have an independent device configuration including the power supply. However, in this configuration, since inter-system communication is performed in a program mode, a procedure is required, and inter-system data transfer takes time, and the CPU is occupied for a long time.

[Problem that the invention attempts to solve]

As described above, while the conventional multiplexing processing devices have advantages, they also all have disadvantages.

An object of the present invention is to provide a multiplexing processing device that has both the advantages of the above-mentioned conventional techniques and eliminates the disadvantages of each.

[Means for solving problems]

To achieve this objective, the multiplexing processing device of the present invention includes: a plurality of processing devices 1, 4; memories 2, 5 coupled to each of the processing devices 1, 4 via buses 3, 6; memory access devices 11-1 and 12-1 connected between the buses 3 and 6 for accessing the memory 2 on the processing device 1 side from the processing device 4; The memory access devices 11-2 and 12-2 are provided for accessing the memory 5 on the processing device 4 side from the processing device 1, and the memory access devices 11-1 and 12-1 include:
A memory address register 2 for writing the address of the memory 5 on the side of the processing device 4 from the processing device 1
1, an output buffer register 22 for writing data to be transferred to the memory 5 on the processing device 4 side, a command register 33 for generating a read command to the memory 5 on the processing device 4 side, and the processing device 4 an input buffer register 34 for storing data read from the side memory 5;
The memory access device 11-2, 12-2 comprises:
A memory address register 2 in which the processing device 4 writes the address of the memory 2 on the processing device 1 side.
1', an output buffer register 22' for writing data to be transferred to the memory 2 on the processing device 1 side, and a command register 33' for generating a read command to the memory 2 on the processing device 1 side.
and an input buffer register 34' for storing data read out from the memory 2 on the processing device 1 side.

〔Example〕

Examples will be described below.

FIG. 2 is a block diagram showing the configuration of one embodiment of the multiplexing processing device of the present invention. In the figure, the numbers 1, 2, 3, 4, 5, and 6 represent the first
This is not different from the case in FIG. 11,12
is the memory access unit (BCC). BCC1
1 is main BCC (BCCM) 11-1, secondary BCC
(BCCS) Consists of 11-2, BCC12 is the secondary BCC
(BCCS) 12-1, Main BCC (BCCM) 12-2
are connected to their own buses 3 and 6, and are connected to BCCM 11-1, BCCS 12-1, and BCCS 12-1 through external lines 13 and 14, respectively.
BCCM 12-2 and BCCS 11-2 are connected.

Now, for example, when communicating from system A to system B, the operation is performed as follows. First, CPU 1 of system A sets the address of memory 5 of system B to BCCS1.
Write in 2-1. Next, CPU1 is BCCS12-1
Write the data to be transferred to. After writing the address and data, the BCCS 12-1 writes the data to the specified address in the memory 5 in direct memory access (DMA) mode. B-type
The CPU 4 can access the memory 5 of its own system and receive the transferred data. The above is a case where communication is performed from system A to system B, but communication from system B to system A can be performed using exactly the same procedure.

FIG. 3 is a block diagram showing one embodiment of a memory access device. In the figure, as an example, BCCM11-1 belongs to the A system and BCCM11-1 belongs to the B system.
Only BCCS12-1 is shown.

First, when communicating from system A to system B, A
The address of the B-system memory 5 specified by the system CPU 1 is sent from the BCCM 11-1 to the BCCS 12-1, and is stored in the memory address register (MAR) 2.
Written to 1. Further, data to be transferred from system A to system B is sent from BCCM 11-1 to BCCS 12-1 and written to output buffer register (OBR) 22. MAR21 and
Writing to the OBR22 is performed in a time-sharing manner according to instructions from the address decoder 31 provided in the BCCM11-1. At the same time as writing to the MAR21 and OBR22, writing to the DMA control circuit 23
starts. After activation of the direct memory access (DMA) control circuit 23, the CPU 1
Under the control of the DMA control circuit 23, the data written to the OBR 22 is written to the memory 5 in accordance with the address written to the MAR 21 in the DMA mode. Device status register (DSR) 32 in BCCM11-1
is provided, and during DMA transfer, a busy indication is displayed on the OSR 32 and the CPU 1 is notified.

On the other hand, when the A system attempts to receive communication from the B system, the A system's CPU 1 reads the address of the B system's memory 5 to be read via the BCCM 11-1.
Write to MAR21 of BCCS12-1. At the same time, a read command is issued from the command register (CMR) 33 in the BCCM 11-1, which activates the DMA control circuit 23 of the BCCS 12-1.
The data corresponding to the address written to the MAR 21 in the DMA mode under the control of the input buffer register 3 is read from the memory 5 and written to the input buffer register (IBR) 34. A-series CPU1 is
By accessing the IBR 34 and reading its contents, it is possible to receive communications from the B system.

The above explained the case where system A sends or receives communication to system B under the initiative of system A, but similarly, system B sends or receives communication to system A under the initiative of system B. If you receive it, BCCM1
2-2, communication can be performed in exactly the same way using the BCCS 11-2.

In other words, although not shown, BCCM12-
2 is the address decoder 31 of BCCM11-1,
Device status register (DSR) 3
2. Corresponding to command register (CMR) 33 and input buffer register (IBR) 34, address decoder 31', device status register (DSR) 32', command register (CMR) 33', input buffer
Equipped with register (IBR) 34', BCCS11-2 is
Memory address register (MAR) 2 corresponds to memory address register (MAR) 21, output buffer register (OBR) 22, and DMA control circuit 23 of BCCS12-1.
1', an output buffer register (OBR) 22', and a DMA control circuit 23', and the functions and operations of these parts are the same as those of the corresponding parts.

[Effect of idea]

In this way, in the multiplexing processing device of the present invention, when sending data to the other party's system, the memory address of the other party is set in the other party's MAR, and
By reading data into the other party's OBR, data can be transferred to the other party's memory using DMA operation. When receiving data from the other party's system, the other party's memory address must be set to the other party's MAR. By sending a read command, data can subsequently be received by the own IBR through DMA operation. In this way, there is an advantage that no procedure is required for data transfer between systems.
Furthermore, since both systems have the same configuration, each system can have an independent device configuration, and furthermore, both systems can have their own communication memories for duplication.

The method of the present invention can be extended to multiple systems by arranging the BCC connections in a star format.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional multiplexing processing device, FIG. 2 is a block diagram showing the configuration of an embodiment of the multiplexing processing device of the present invention, and FIG. 3 is an embodiment of a memory access device. FIG. 1...Central processing unit (CPU), 2...Memory,
3...Bus line, 4...Central processing unit (CPU), 5
...Memory, 6...Bus line, 7...Common memory,
8, 9...Digital input/output circuit (DIO), 11
...Memory access device (BCC), 11-1...
Main BCC (BCCM), 11-2……Secondary BCC
(BCCS), 12... Memory access device (BCC), 12-1... Secondary BCC (BCCS), 12-
2...Main BCC (BCCM), 13, 14...External line,
21...Memory address register (MAR),
22... Output buffer register (OBR), 23... DMA control circuit, 31... Address decoder, 32... Device status register (DSR), 33... Command register (CMR), 34... …Input/Buffer/
Register (IBR).

Claims (1)

[Claims for Utility Model Registration] A plurality of processing devices 1 and 4, memories 2 and 5 connected to each of the processing devices 1 and 4 via buses 3 and 6, and memories connected between the buses 3 and 6. , memory access devices 11-1 and 12-1 for accessing the memory 2 on the processing device 1 side from the processing device 4, and the buses 3 and 6, and are connected between the processing device 1 and the processing device 4. and memory access devices 11-2 and 12-2 for accessing the side memory 5, and the memory access devices 11-1 and 12-1 are provided with:
A memory address register 2 for writing the address of the memory 5 on the side of the processing device 4 from the processing device 1
1, an output buffer register 22 for writing data to be transferred to the memory 5 on the processing device 4 side, a command register 33 for generating a read command to the memory 5 on the processing device 4 side, and the processing device 4 an input buffer register 34 for storing data read from the side memory 5;
The memory access device 11-2, 12-2 comprises:
A memory address register 2 in which the processing device 4 writes the address of the memory 2 on the processing device 1 side.
1', an output buffer register 22' for writing data to be transferred to the memory 2 on the processing device 1 side, and a command register 33' for generating a read command to the memory 2 on the processing device 1 side.
and an input buffer register 34' for storing data read out from the memory 2 on the processing device 1 side.