JPS5816326A - Data channel controlling system - Google Patents

Abstract

PURPOSE:To obtain an economical data channel device, by providing the memories that store the channel words using an input/output device in a time division way and in the number equal to the input/output devices which are actually used at one time. CONSTITUTION:A data channel device receives an input/output instruction from a CPU and then a control part 12 puts the data of IOA on a writing bus 13. This data is set to an IOA buffer 4. Then an idle bit position of an idle bit register 1 of a channel word CHW is detected by a detecting circuit 3, and the address of a CHW memory 9 is written into a CHW address memory 6. The contents of the memory 6 are read by a CHWA memory reading signal 8 to know the address of the memory 9, and 1 is written to the bit of the register 1 corresponding to the address of the memory 9. After this, the corresponding IOA is set to the buffer 4 with each reception of the data and then read and written out/into the memory 9. The transfer is controlled between an input/output device and a storage device by the contents of the memory 9. Accordingly it is not necessary to have the CHW memories equivalent to the maximum number of the input/output devices.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for time-sharing control of a plurality of input/output devices of a data channel device of an electronic computer.

In the prior art, in a multiplexer channel device that controls multiple input/output devices in a time-sharing manner, a channel word (
C) (hereinafter referred to as IIV) consists of a single output device and several words, and has as many CHWs as the logical maximum number of input/output devices. An example is shown in FIG. In Figure 1, G
W consists of 4 words corresponding to the input/output device, and stores command/word address (cm), device status (DOT), channel status (C8T), number of words (WE), data address (DA), data (DATA), etc. I'm letting you do it. Since the other GW has the maximum number of input/output devices (for example, 256), the memory for storing this CHW is 4 words x 256-1024 words.

However, since the number of input/output devices actually connected to a data channel device is several tens at most, there is a drawback that most of the primary memory is unused. This drawback becomes noticeable when the ON memory is provided within the data channel device in order to reduce the access frequency of the main memory, and it is difficult to adopt a system in which the external memory is provided within the data channel device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a more economical data channel device that eliminates the drawbacks of the prior art built-in data channel system described above.

In the present invention, in order to eliminate the drawbacks of the prior art, a memory for storing a criminal memory address indicating a correspondence between an input/output device address and a CI (N memory), and a memory for storing a criminal memory address (C indicating an empty G memory) are provided.
It is characterized in that it is equipped with empty registers and CHW memories are installed as many as the number of input/output devices that are actually used simultaneously.

Specific examples of the present invention are shown in FIGS. 2 and 3. Figure 2 shows channel word address (cHwA) memory (a) channel word (
The configuration of cHw) memory (b), channel word (OIw) empty register (C) is shown. (g) Kneeling memo IJ(a) consists of 256 words (1 word 4 bits) which is the logical maximum number of input/output devices (for example, 256), and since IOA+n is the uA memory content is 0, IOA+n is stored at address 0 in the memory. It shows that there is a storehouse. The CHW memory (b) consists of 4 words for a single person output device, and its contents are the same as those of the prior art. This external memory consists of the number of input/output devices actually used simultaneously (for example, 10), that is, 4 words x 10 - 40 words. The CHW empty register (C) consists of 10 bits, and each bit is associated with whether the C)N memory is empty or in use, and when it is 1, it is in use, and when it is 0, it is empty. FIG. 3 shows a part of a data channel device using the present invention, and 1 is [
Empty register, 2 is CHW empty register control signal, C) I
Controls reading and writing of W empty register 1. Reference numeral 3 designates an empty bit position detection circuit which inputs the output of the empty register 1, detects the empty bit position of the CHW empty register, and outputs a bit number.

4 is the IOA used when accessing CHWA memory
It is a buffer. 5 is the IOA buffer control signal
Used when setting IOA to buffer 4. 6 is an MA memory which is accessed using the empty bit position detection circuit 5 as input data and the IOA buffer 4 as an address. (g) The memory always outputs the contents indicated by the IOA buffer 4. 7 is a busy memory write signal, which is used when writing to the memory 6. 8 is a memory read signal used to read the contents of the memory, and 9 is a memory read signal which is accessed using the output of the memory 6 as an address and the write bus 13 as input data. Reference numeral 11 is a CHW memory control signal for the trigger memory 9, which controls reading and writing of the trigger memory 9. 12 is a control section of the data channel device. 13 is G station empty register 1. IOA
Buffer 4. c) A write bus for transmitting data to the 1W memory 9, and a read bus 14 used to read data from the pull memory 6 and the cImA memory 9.

Hereinafter, the present invention will be specifically explained using FIGS. 2 and 3. When the data channel device receives an input/output command from the central processing unit, it determines an IOA-compatible master. First, the control unit 12 puts IOA data on the write bus 13, outputs a signal to the write bus 5, and sets the IOA in the IOA buffer 4. Furthermore, when a write is instructed to the signal 7, the data indicated by 1.3, that is, the address of the memory is written to 6. Furthermore, -IOA is set to 4, the contents of 6 are read by 8, the address of the 0 station memory is known, and 1 is written to the bit of the [empty register] corresponding to this address. Thereafter, the corresponding IOA is set in the IOA buffer 4 each time data is exchanged, and 11 reads and writes to the memory 9. Transfer control between the well-known input/output device and the storage device is performed based on the contents of the memory 9.

When the input/output command is completed, IOA is set to 4, a pull memory read signal 8 is issued, the address of the GWN memory is read from the memory 6, and 0 is written to the bit position of the GF empty register 1 corresponding to this address. Finish processing all input/output instructions.

According to the present invention, it is only necessary to provide as many memories as the maximum number of input/output devices that can be used simultaneously, eliminating the uneconomical nature of the conventional technology of providing C)N memories corresponding to the logical maximum number of input/output devices, and making the data channel device more economical. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing [ of the prior art, FIG. 2 is a diagram showing the 0-station memory and GW empty register of the present invention, and FIG. 3 is a diagram showing a specific example of the circuit of the present invention. . 1... G empty register 2... CHW empty register control signal 3... Empty bit position detection circuit 4... IOA buffer 5... IOA buffer control signal 6... ai A memory 7. ... (G) Sleeping memory write signal 8 ... (G) Mock memory read signal 9 ... Stop memory 11 ... G station memory control signal 12 ... Control unit 13 - Write bus 14 ... Lead bus No. 1 Figure f-2 h) (4) '''8-3 Figure 2

Claims (1)

[Claims] 1 In a data channel device that directly exchanges information between multiple input/output devices and storage devices based on instructions from the central processing unit, independently of the central processing unit, the input/output devices are used in a time-sharing manner. A memory for storing channel words, which are management information necessary for the purpose of the above, for a plurality of input/output devices, a channel word register indicating whether an area of the memory is empty or in use, and an input/output device used according to instructions from the central processing unit. A data channel control method, characterized in that a corresponding channel word is set as an area of a channel word memory corresponding to an empty bit in the register in the channel word, and a memory is provided for storing the address.