JPS6068461A - Memory multiplex access device - Google Patents

Abstract

PURPOSE:To shorten an access time by delivering a common memory access signal outputted independently of each other through a control circuit in prescribed timing to access a common memory. CONSTITUTION:When the p-th processor delivers a data write request to the common memory 1, the data is stored to a write data register 17, and the corresponding address is stored to an address register 20 respectively. These data and address are written to the memory 1 by a time division sampling signal delivered from a control circuit 26. Then the m-th processor delivers a data read request, and the address data is stored to an address register 21 and then transferred to a memory address register 25 by a time division sampling signal given from the circuit 26. Then data area read out of the memory 1 and read by the m-th processor via a read data register 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a memory multiple access device that accesses a common memory.

[Background technology]

In information processing, communication control processing, etc., when a single processor has speed problems or when functions become complex, multiple processors are used to solve the problem. The common memory access method, which is one type of access method, has the following problems.

FIG. 1 shows a conventional memory multiple access system.

/ is a common memory, and 2 and 3 are processors P, .P, which access the common memory / in multiple ways. Also t
~/lI- is a buffer or register for preventing collision of signals on the bus, and /lI- is a control circuit for controlling the sequence of operations of these buffers or registers or the processor.

Next, the operation of the conventional example will be explained. When accessing the memory, for example, performing a read operation, the processor/control circuit/S
First, a request signal is sent. Next, the control circuit/
The ACK signal (DataReady) from 3 is checked, and if it is in the ready state, data can be read from the memory. A similar sequence applies to write operations. When accessing the memory in this way, software operations such as sending a request signal and resetting are required. By the way, when a common memory is accessed by a plurality of processors, the above sequence is required for each processor, so the conventional method has the disadvantage that the access time becomes extremely long and the control circuit becomes complicated.

[Purpose of the invention]

The present invention has been proposed in view of the above-mentioned drawbacks of the prior art, and it is an object of the present invention to provide a memory multiplexing device with a simple configuration and short access time.

[Structure of the invention]

In the present invention, write command signals and read command signals output from m processing devices are input, and according to these input signals, m time division sampling signals for write data, 9m time division sampling signals for read data, and 1m time division sampling signals for read data are input. a control circuit that outputs a time-division sampling signal for address designation, a write pulse signal for common memory, and a load pulse signal in a predetermined order; 7 of the write data according to the time division sampling signal
A time division register for write data that selectively outputs one of the address designation data, and address designation data output from the m processing devices are input, and one of the address designation data is selectively output according to the time division sampling signal for address designation. a common memory for storing write data output by the write data time division register in accordance with the addressing data output from the address designation data time division register; and a common memory for storing the write data output by the write data time division register; The data read out from the common memory is inputted according to the addressing data output from the time division register and the load pulse signal outputted from the control circuit, and the data read out from the common memory is selectively sent to a predetermined processing device according to the time division sampling signal for read data. It is composed of a time division register for read data to be outputted to and K.

〔Example〕

The configuration of a memory multiple access device according to an embodiment of the present invention will be described with reference to the drawings. Figure 2 is a diagram showing its configuration, in which m external processors are connected to a common memory/
Shows when accessing. Each processor has a data bus having a /data S bit configuration, an address bus having a /data l bit configuration, a 1ζ write request signal, and a read request signal. 10/[PDB1]
is the i-th signal of the data bus of the P-th processor, /θJ (PRR) is the read request signal output from the P-th processor, /θ3 (PWR) is the write request signal output from the P-th processor, /ni l
[:PA] is the j-th bit signal of the addressing data output from the P-th processor.

, 26 is a control circuit which receives write request signals (IWR-mWR) and read request signals (IWR-mRR) output from each processor, and specifies addresses in a predetermined order in synchronization with the master clock signal (CK). time division sampling signal (/ASo-mA80
), time division sampling signal for write data (/S
TO~m5To), time division sampling signal for read data (/DTO-mDTo), write pulse signal (3) for common memory and load pulse signal (
L) is output.

20 is a register that holds the j-th bit address data output from the P-th processor, and performs memory operation in synchronization with the write request signal or read request signal output from the P-th processor, and performs time-sharing for address specification. Data is transferred using a sampling signal (PASO).

2/ is a similar register that holds the j-th bit address data output from the m-th processor. 2 The left is l
It is a memory address register for bit inputs (I, ~I!,), and the j-th input (Ij) is the j
It is connected to the Q output of the bit-th address register.

/ is a common memory that is accessed multiplexed by each processor, and has an 1-bit address input, an S-bit data input, and an S-bit data output. The l-bit address inputs are each connected to the l-bit outputs (Ql to Qt) of the memory address register 2S.

/ is a register that holds the 1st bit write data output by the P-th processor, performs memory operation in synchronization with the write request signal output by the P-th processor, and performs time-division sampling for ηW write data. Data is transferred by the signal (PSTO). /9 is a similar register that holds the i-th bit write data output from the m-th processor. 23 is a memory write register for S bit input (I, ~S), i
The bit-th input (Ii) is connected to the Q output of the i-th bit address register of each processor.

Also, the Q output (Ql to QS) of the memory write register 23
) are the data of common memory/manpower (11~Is
)It is connected to the.

2da is an S-bit input memory read register that holds the output data of the common memory / in synchronization with the load pulse signal output from the control circuit 2B.

/B is the time division sampling signal for read data (PD
This is a register for the P-th processor that holds Qi output data of the memory read register 29 in synchronization with TO), and the data is transferred to the P-th processor in response to a read request signal (PRR) K. 7g is a similar register for the mth processor that holds the Qi output data of memory read register 2'l.

Next, the operation of the memory multiple access device according to the embodiment of the present invention will be explained. Suppose that there is now a request from the Pth processor to write data to the common memory/. When the write request signal 103 from the P-th processor is input to the clock input VC of the write data register/7, the write data register/7 stores the write data output from the P-th processor. Further, when the write request signal /θ3 input through the OR circuit inputs the clock signal of the address data register 20, the address data register 0 stores the address data output from the P-th processor.

In response to the write request signal input to the control circuit Colo, the control circuit Colo outputs a time division sampling signal for address designation (PSTO) and a time division sampling signal for write data (PASO). The write data in the write data register 17 is transferred to the memory write register by the time division sampling signal for write data (PSTO), and the address data in the address data register 2θ is transferred to the memory address by the address data sampling signal (PASO). register! Transferred to 5. The common memory / becomes ready for write operation by the write pulse signal (5) output from the control circuit 6, and the output data of the memory write register 23 is written to the address position according to the output data of the memory address register 23.

Assume that a data read request from the m-th processor for the common memory/ is immediately followed by a data write request from the P-th processor.

That is, the reading lJ:I t from the m-th processor, the request signal (mRR) is input to the address data register 2/ via the OR circuit 22, so the address data register 2/ receives the address data from the m-th processor. Remember. In addition, read request signal (n+RR
) is also input to the read data register/g and the control circuit U. The control circuit 2B generates a time-division sampling signal (m5To) for address designation at the timing when the above-mentioned write operation ends.

Subsequently, a load pulse signal (L) and a time division sampling signal for read data (mDTQ) are output.

Address data is transferred from the address data register 2/ to the left side of the memory address register 2 by the address designating time division sampling signal (msTo), and the common memory/
Data is read from a predetermined address. After the continued data is stored in the memory read register by the load pulse signal (L), it is transferred to the read data register /g by the read data time division sampling signal (mDTo) K and read by the m-th processor K. In this embodiment, the common memory access signal independently output from each processor is controlled by the control circuit unit 116 at a predetermined timing to access the common memory access signal. be.

[Young fruit of light]

As described above, according to the present invention, the common memory under frequent access by the processor can be accessed m t,r:' as if it were a single access, and this is due to the hardware configuration. It is possible to improve the knowledge 161 of the access time. Also, even if you have 1 multilayer or 1 force, you won't be able to spend time on the force 2 dito like in the past. Also, s(
'JJ) + L8L 1i-, which is only filtrated, has many advantages.

[Brief explanation of the drawing]

11th. A is a conventional example with a multiple access hook iLt.
What is the figure, the second figure is a memory of 1.1 millimeters in Maki Akira's memory! Access m u+f to 6°/...Common memory. ! , 3...processor. Hiro ~/4L...Buffer or register. /! ;, 26...11iIJ valence circuit. /Otsu, /δ...Protrusion data register. /mu/ri...Write data register. -10, J7...Address data register. , /, l... ” Reminiscences of Terikazu. , λ3...Memory, i insert register. , <+...Memory, nine, i, 1. t L,, register. ,! 5... Meshisu gamma dress register. /J/...1st bit data 11-! outputted by the 6th PiJ Hisosa! "01" 1 /U...Pl, ILI processor output T Q
Read request signal No. J. 10, s...P 1'+i' i: Input request signal No. j output from the blobitser of I. / (717,...P fr Address number of j pitro output by the processor of fJ.

Claims (1)

[Claims] Write command signals and read command signals output from m processing devices are input, and time-division sampling signals for m write data and 9m time-division sampling signals for read data are generated in accordance with the input signals. a control circuit that outputs 1 m signals of time-division sampling signals for address designation, write pulse signals for common memory, and load pulse signals in a predetermined order; a write data time division register that selectively outputs one of the write data according to a data time division sampling signal; and a write data time division register that receives address designation data output from the m processing devices and receives the address designation time division sampling. a time-sharing register for addressing data that selectively outputs one of the addressing data in accordance with a signal; and a time-sharing register for write data that outputs one of the addressing data in accordance with the addressing data output from the time-sharing register for addressing data. a common memory for storing write data; and inputting data read from the common memory according to addressing data output from the addressing time division register and a load pulse signal output from the control circuit, A memory multiple access device comprising: a time division register for read data selectively outputting to a predetermined processing device according to a time division sampling signal.