JPH09259598A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device capable of receiving a large amount of storage demand from the CPU without a decline in storage utilization ratio. SOLUTION: A check bit write circuit 33 generates a check bit of data transmitted from a CPU 20, and generates a check bit address on the basis of an address transmitted from the CPU 20. A check bit write cue circuit 34 stores in accordance with each other check bits and check bit addresses generated by the check bit write circuit 33. During a period free of a read demand and a write demand form the CPU 20, the check bit write circuit 33 writes the check bit stored in the check bit write cue circuit 34 to the check bit address stored in the check bit write cue circuit 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device,
In particular, the present invention relates to a storage device having a data error check function and storing check bits in a memory space different from data.

[0002]

2. Description of the Related Art In a storage device, in order to improve the reliability of data, generally, a check bit such as parity or ECC is provided to check a data read error. The correspondence between the check bit and the data to which it corresponds must always be maintained.

Therefore, conventionally, the check bit is stored here, for example, by increasing the size of the corresponding data (for example, 8 bits) by the size of the check bit (for example, 1 bit) (for example, 9 bits). Was there. That is, the check bit is stored and written / read as a part of the data at the same address as the corresponding data.

However, according to this method, the number of signal lines of the memory control circuit of the storage device must be increased by the amount corresponding to the increased data size. That is, it is necessary to use a memory element having a dedicated configuration (for example, x9 bit configuration) to which a check bit is added. On the contrary, when using a storage element having a general configuration (for example, × 8 bit configuration) to which a check bit is not added, a storage element for storing the check bit must be prepared separately from the storage element for storing the data. I won't.

Therefore, a method has been proposed in which a storage area for storing check bits is allocated in advance to a predetermined area in the memory space, and when the corresponding data is read out, the check bit is also read out (for example, JP-A-55-55). 1
No. 658, JP-A-3-184146, JP-A-4-33.
6644). According to this method, it is not necessary to increase the number of signal lines of the memory control circuit of the memory device or to use a memory element having a dedicated structure, and even if a memory element having a general structure is used, a memory for storing check bits is stored. There is no need to prepare an element.

[0006]

According to the above-mentioned method,
Since the check bit is stored separately from the data in the memory space, there are the following problems.

When this system is applied to a memory capable of writing / reading such as DRAM, SRAM and flash memory, the address is not fixed unlike ROM (read only memory), so that the check bit and the data are mutually exchanged. It is necessary to perform writing / reading while maintaining the correspondence relationship with.

Writing / reading while maintaining the correspondence between the check bits and the data can be performed by software, for example. However, in the case of software, a dedicated C for the memory control circuit of the storage device
It is necessary to provide a PU, and this is an obstacle to improving the writing / reading speed.

On the other hand, writing / reading while maintaining the correspondence between the check bits and the data can be performed by hardware. However, even when using hardware, when writing data,
It is still necessary to perform the check bit write operation in addition to the data write operation. Therefore, until these two write operations are completed, CP
Next memory request from U (write / read request)
Could not be accepted.

Apart from the above, according to the above-mentioned method, there are the following problems depending on the check bit storage method in the memory space. The size of the check bit (eg 1 bit) is usually smaller than the size of the data to be accessed (eg 8 bits). On the other hand, the entire memory space has the same configuration (for example, x8).
It is usually configured by a memory element having a bit configuration). For this reason, the check bits are stored in the storage area for storing the check bits in the memory space by using only a part of the storage area having the same size as the size of the data, or some check bits are stored. It is necessary to store the bits collectively as a data string having the same size as the data size.

In the former case, a large unused space is generated, and the utilization efficiency of the memory as a resource is lowered, so that it cannot be actually adopted. In the latter case, on the other hand, the memory is maximally utilized. However, when writing (writing) only one piece of data, a plurality of check bits that have the same size as the size of the data are once read (read) from the memory, and the check bits of the data to be written. Only after rewriting, it is necessary to write to the memory again. That is, a so-called read modify write operation is required. Therefore, the writing performance to the memory is significantly reduced.

An object of the present invention is to provide a storage device having an error check function capable of accepting a large number of memory requests from a CPU without degrading the memory utilization efficiency and the memory writing performance. .

Further, the present invention provides a storage device having an error check function capable of speeding up a data read operation from a memory including a check bit without deteriorating a memory utilization efficiency and a memory write performance. The purpose is to do.

[0014]

FIG. 1 is a block diagram of the principle of the present invention, showing the configuration of a storage device 100 according to the present invention.
The storage device 100 includes a memory 40 that stores data and check bits corresponding to the data at different addresses, and a CP.
The memory control circuit 30 is connected to the U20 and executes a read request and a write request to the memory 40 from now on. The memory control circuit 30 includes a check bit write circuit 33 and a check bit write queue circuit 34.

The check bit write circuit 33 has a CP
A check bit corresponding to this is generated based on the data sent from U20, and a check bit address for storing the generated check bit is generated based on the address corresponding to the data sent from CPU20. Write check bit to address. The check bit write queue circuit 34 stores the check bit and check bit address generated by the check bit write circuit 33 in association with each other. CP
The check bit write circuit 33 stores the check bit stored in the check bit write queue circuit 34 in the corresponding check bit write queue circuit 34 during the period when there is no read request or write request from the U20 to the memory 40. Write to the check bit address.

According to the storage device of the present invention, the check bit generated based on the data sent from the CPU 20 and the check bit address generated based on the address corresponding to the data sent from the CPU 20 are:
The check bit write queue circuits 34 are associated with each other and temporarily stored.

Therefore, the memory device of the present invention can perform writing and reading while maintaining the correspondence relationship between the check bit and the data by the hardware called the check bit write queue circuit 34. Thereby, the execution speed of writing and reading of the memory 40 can be improved.

Further, in the memory device of the present invention, since the check bit and the check bit address are temporarily held in the check bit write queue circuit 34,
It is not necessary to continuously write the check bit after writing the data. Therefore, the writing speed of the memory 40 can be improved. As a result, the next write request and read request from the CPU 20 can be accepted without writing the check bit as long as the writing of the data is completed.

Further, in the storage device of the present invention, since the check bit and the check bit address are temporarily held in the check bit write queue circuit 34,
The writing of the check bit can be executed during the period when the memory request is not issued from the CPU 20.
That is, the writing of the check bit is a writing operation that is hidden and invisible from the CPU 20. Therefore, writing the check bit does not hinder the execution of the memory request from the CPU 20. As a result, even if a method in which the data and the check bit corresponding to the data are stored in different addresses in the memory 40 is adopted, the writing performance to the memory 40 does not deteriorate.

According to the storage device of the present invention, by adopting the method of storing the data and the check bit corresponding thereto in the memory 40 at different addresses, the utilization efficiency of the memory is prevented from being lowered and the CPU 20 Many memory requests can be accepted, and the performance of the memory 40 seen from the CPU 20 can be improved.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 2 is a block diagram of a storage device, showing the configuration of a storage device 100 of the present invention. In FIG. 1, the storage device 100 is connected to the CPU 20 via a data bus, an address bus, and a control bus.

The CPU 20 sends a read request and a write request for the memory 40 to the storage device 100 or the memory control circuit 30. In the read request, the address to be read is also sent. In the write request, the data to be written and its address are also transmitted.

The memory control circuit 30 is connected to the CPU 20, and exchanges addresses (address signals) with the CPU 20 via the address bus, exchanges data with the data bus, and transmits via the control bus. Sends and receives various control signals. The error response (error response signal) sent from the memory control circuit 30 is sent to the CPU 20 via the control bus. The CPU 20 sends a read request and a write request to the memory 40 to the memory control circuit 30 via the control bus. The memory control circuit 30 executes a read request and a write request of the memory 40.

The memory control circuit 30 is connected to the memory 40, exchanges addresses with the memory 40 via a (local) address bus, exchanges data with a (local) data bus, ) Sending and receiving various control signals via the control bus. The memory control circuit 30 sends a read request and a write request to the memory 40 via the control bus, and executes the read request and the write request of the memory 40 requested by the CPU 20.

The memory control circuit 30 includes a read / write control circuit 31, a data write circuit 32, a check bit write circuit 33, a check bit write queue circuit 34, a read circuit 35, an error processing circuit 36, and a password circuit 37.

The read / write control circuit 31 refers to the check bit write queue circuit 34 to control each of the other circuits of the memory control circuit 30 to read / write the memory 40. Data writing circuit 32
Writes data to a specified address in the data space 41 of the memory 40. Check bit writing circuit 33
Generates a check bit and a check bit address, and writes the check bit to the check bit address in the check bit space 42 of the memory 40. The check bit write queue circuit 34 temporarily stores the check bit and check bit address generated by the check bit write circuit 33. Readout circuit 3
Reference numeral 5 reads data from the data space 41 of the memory 40, and reads a plurality of check bits (check bit data) from the check bit space 42. The error processing circuit 36 performs an error check using the data read by the read circuit 35 and the check bit selected from the check bit data read by the read circuit 35 or the check bit stored by the check bit write queue circuit 34. . The password circuit 37 is previously stored in the memory 4
The password stored in 0 is set (released).

The memory 40 stores data and check bits corresponding to the data at different addresses. That is, in the memory 40, the data is stored in the data space 41,
The check bit is stored in the check bit space 42. The data space 41 and the check bit space 42 are separated by addresses in the memory space of the memory 40. The check bits are stored at the same address as a set of a plurality of check bits (check bit data). The reading and writing of check bits are performed in units of check bit data. The check bit data is a data string in which a plurality of check bits corresponding to a plurality of data are collected and have the same size as one data.

The memory 40 is a storage element (RAM) capable of writing and reading, and is composed of, for example, a flash memory. Therefore, in order to write, it is necessary to set (cancel) the password stored in advance.
The memory control circuit 30 includes a password circuit 37. Therefore, when the memory 40 is a DRAM or SRAM, the password circuit 37 is omitted.

FIG. 3 shows the structure of the memory 40. As shown in FIG. 3, in the data space 41 of the memory 40, eight data D0 to D7 are assigned to addresses X'n0000 to X'n0007.
Is stored. In this example, data stored at the same address is called one piece of data. One piece of data (its size) consists of 8 bits.

The check bit is 1 for parity check.
Consists of bits. Check bits P0 to P7 correspond to the data D0 to D7, respectively. Data D0 to D7
The eight check bits P0 to P7 corresponding to are combined into one check bit data. The check bit data is stored at the same address X'nppp0 in the check bit space 42. It is not necessary that the address X'nppp0 of the check bit data continues to the last address X'n0007 of the data D0 to D7.

In the check bit data of the address X'nppp0, the smallest address X'of the data D0 to D7.
The check bit P0 of the data D0 having n0000 is the least significant bit, and the check bit P7 of the data D7 of the maximum address X'n0007 is the most significant bit. That is, the position of each check bit in the check bit data is
It is determined by (the value of the least significant bit) of the data corresponding to the check bit. This relationship is always maintained by the hardware.

FIG. 4 shows the configuration of the memory control circuit 30 excluding the password circuit 37. As shown in FIG. 4, the memory control circuit 30 includes a timing circuit (TG) 1, an address conversion circuit 3, an address queue 4, an address comparison circuit 2, a multiplexer 5, a check bit generation circuit 6, a check bit queue 7, and a read modify. Light circuit (RM
W) 11, a multiplexer 8, a multiplexer 9, and an error check circuit (ECC) 10.

The read / write control circuit 31 comprises a timing circuit 1 and an address conversion circuit 3. The data write circuit 32 includes the multiplexer 5 and the multiplexer 8.
Consists of The check bit write circuit 33 includes an address conversion circuit 3, a check bit generation circuit 6, a multiplexer 5, a multiplexer 8 and a read modify write circuit 11. The check bit write queue circuit 34 includes an address queue 4 and a check bit queue 7. The read circuit 35 includes the multiplexer 5. The error processing circuit 36 includes a multiplexer 9 and an error check circuit 10.

The timing circuit 1 takes in various control signals sent from the CPU 20, and based on this, the control signals of the other circuits of the memory control circuit 30 and the memo 40.
Control signal is formed at a predetermined timing and sent to them. As a result, the timing circuit 1 becomes the CPU 2
Memory request from 0 (write request and read request)
Execute

The address conversion circuit 3 is the timing circuit 1.
In accordance with the control signal from, the address corresponding to the data to be read and written is taken in, and the check bit address of the check bit corresponding to the data is generated (converted) and output based on this.

When there is a write request from the CPU 20 to the memory 40 in accordance with the control signal from the timing circuit 1, the check bit generation circuit 6 fetches the data sent from the CPU 20 and performs a predetermined operation, thereby A check bit corresponding to this is generated and output based on the data.

The address queue 4 temporarily stores the check bit address generated by the address conversion circuit 3.
The check bit queue 7 temporarily stores the check bit generated by the check bit generation circuit 6. The address queue 4 and the check bit queue 7 are formed of a FIFO buffer having a predetermined number of stages, have unit circuits with the same number of stages, and have a size capable of storing the same number of addresses and check bits. The unit circuit of the address queue 4 has a data width of 8 bits, and the unit circuit of the check bit queue 7 has a data width of 1 bit. In addition, FIFO
A shift register may be used instead of the buffer.

The two FIFO buffers, which are the address queue 4 and the check bit queue 7, store the check bit and the check bit address in association with each other according to the control signal from the timing circuit 1, and store them at the head (the multiplexer 5 and the read). The check bit address and the check bit existing on the modify write circuit 11 side) are output to the multiplexer 5 and the read modify write circuit 11, respectively. Further, the check bit queue 7 outputs to the multiplexer 9 the check bit corresponding to the check bit address which is coincident with the result of the comparison in the address comparison circuit 2 among the check bits stored therein according to the control signal from the timing circuit 1. .

The address comparison circuit 2 is the timing circuit 1
According to the control signal from the memory 40 from the CPU 20
When there is a read request to the check bit address, the check bit address generated by the address conversion circuit 3 is compared with each of the check bit addresses stored in the check bit queue 4. As a result of the comparison, the address comparison circuit 2 sends a match signal and a mismatch signal to the timing circuit 1 when there is a matching check bit address and when there is no matching check bit address (no matching).

The multiplexer 5 selects one of the address output from the address queue 4 and the address from the CPU 20 (or the check bit address output from the address conversion circuit 3) according to the control signal from the timing circuit 1. Output. The address output from the multiplexer 5 is input to the memory 40.

The multiplexer 8 receives the (new) check bit data output from the read-modify-write circuit 11 and C in accordance with the control signal from the timing circuit 1.
Either one of the data from the PU 20 is output alternatively. The data output from the multiplexer 8 is the memory 40.
Is input to

The multiplexer 9 selectively outputs either the check bit output from the check bit queue 7 or the check bit output from the memory 40 according to the control signal from the timing circuit 1. Actually, the multiplexer 9 selects the check bit (1 bit) to be used for the error check from the check bit data (8 bits) sent from the memory 40. That is, the check bit used for the error check is selected based on the address (value of the least significant bit) of the read request from the CPU 20.

The error check circuit 10 uses the check bit output from the multiplexer 9 (the check bit corresponding to the data) and the data from the memory 40 in accordance with the control signal from the timing circuit 1 to generate an error regarding the data. Check. The error check circuit 10 sends an error response to the CPU 20 if an error is found by the error check, and does not send an error response if no error is found.

The read-modify-write circuit 11 modifies (exchanges) the check bit data using the check bit output from the check bit queue 7 and the check bit data from the memory 40 according to the control signal from the timing circuit 1. And output. That is,
From the check bit data (8 bits) from the memory 40, the check bit at the bit position where the check bit is to be written is selected and changed to the check bit to form new check bit data. For this selection, for example, the value of the least significant bit (1 bit) of the address of the write request from the CPU 20 is added to each check bit in the check bit queue 7.

Next, the write operation in the memory device 100 will be described with reference to FIGS. FIG. 5 is a diagram showing a write operation in the storage device 100. When there is no space in the check bit write queue circuit 34, the timing circuit 1 sends a busy signal to the CPU 20 and does not accept the memory request, and writes the check bit stored in the check bit write queue circuit 34 (check bit Write cycle) is executed with priority. The check bit write cycle will be described later.

Therefore, in the check bit write queue circuit 34 (one of the address queue 4 and the check bit queue 7), for example, a flag is added to the unit circuit. When the check bit address or check bit is written in the corresponding unit circuit, the corresponding flag is turned on (“1” or high level). Last (address conversion circuit 3 and check bit generation circuit 6
The timing circuit 1 sends out a busy signal in response to turning on of the flag corresponding to the unit circuit (side).

The CPU 20 requests the memory control circuit 30 of the storage device 100 to write to the memory 40 (C
PU-WRITE) and sends the address A0
(X'n0000 in FIG. 3) and data D0 are transmitted.

When there is a write request to the memory 40, the timing circuit 1 executes the write request (write cycle) because the check bit write queue circuit 34 has a space because it does not send a busy signal. . That is, various control signals necessary for writing data are formed to cause the data write circuit 32 to write data.

The timing circuit 1 forms a write request (RAM-WRITE) to the memory 40 and sends it to the memory 40. At the same time, the multiplexer 5 and the multiplexer 8 under the control of the timing circuit 1 take in the address A0 and the data D fetched in the memory control write 30.
0 is sent to the memory 40. As a result, in the memory 40, the data D0 corresponds to the address A0 (X'n0000).
) Is written. The timing circuit 1 sends a write end (CPU-ACK) to the CPU 20. This completes the write memory cycle (write cycle).

When the write cycle is executed, the timing circuit 1 executes the check bit DP0 and the check bit DP0 for the data D0 to be written in the check bit write circuit 33 in parallel (or as part of the write cycle). The check bit address AP is generated and stored in the check bit write queue circuit 34. Therefore, the timing circuit 1 receives the fetched address A0 and data D in the write cycle.
0 is the address conversion circuit 3 and the check bit generation circuit 6
To enter.

The address conversion circuit 3 generates an address (check bit address) AP (X'nppp0 in FIG. 3) in which a check bit should be written based on the address A0. The check bit address AP is stored in the address queue 4. The check bit generation circuit 6 uses the data D0
The check bit DPn (P0 in FIG. 3 which is new, hereinafter P0 ′) is generated based on The check bit DPn is stored in the check bit queue 7.

The check bit address AP and the check bit DPn are stored in the address queue 4 and the check bit queue 7 in order from the unit circuit on the most front side where the flag is not turned on. The check bit address AP and the check bit DPn are stored in the address queue 4 and the check bit queue 7 until the check bit DPn is written in the memory 40 (the read modify write ends).

By the end of the write memory cycle,
The memory control circuit 30 and the memory 40 are in a state of waiting for a memory request to the CPU 20. Here, when there is a memory request from the CPU 20, the timing circuit 1 executes this. Therefore, it is possible to receive and execute the next memory request immediately after writing the data without ending the writing of the check bit.

If the memory request is a write request, the write cycle is repeated. When the memory request is a read request, a read cycle shown in FIG. 6 or 7 described later is performed. As can be seen from this, the write cycle and the check bit write cycle are not necessarily performed continuously as shown in FIG. FIG.
For convenience, these are shown in the same drawing.

When there is no memory request from the CPU 20, the timing circuit 1 has the check bit address and the check bit stored in the check bit write queue circuit 34 (the flag corresponding to the head unit circuit is on). At the same time, writing of the check bit (check bit write cycle) is automatically executed. That is, various control signals necessary for writing the check bit are formed and the check bit writing circuit 33 is made to write the check bit.

The timing circuit 1 forms a read request (RAM-READ) to the memory 40 and sends it to the memory 40. At the same time, by controlling the timing circuit 1,
The address queue 4 outputs the check bit address AP (X'nppp0) at the head thereof, and the multiplexer 5 sends this to the memory 40. As a result, in the next cycle, the check bit data DP0 stored in the address A0 from the memory 40 (P7 to P7 in FIG. 3).
0) is read.

The check bit queue 7 and the read modify write circuit 11 are controlled by the timing circuit 1.
The check bit data DP0 read by is modified. That is, the check bit queue 7 outputs the check bit DPn (P0 ′) at the head thereof. The read-modify-write circuit 11 takes in the check bit data DP0 (P7 to P0) and the check bit DPn (P0 '), and converts the predetermined bit P0 of the check bit data DP0 into the check bit DPn (P
0 ') (exchange). At this time, since the value of the least significant bit of the address stored in the check bit queue 7 corresponding to the check bit DPn (P0 ') is "0", the least significant bit P0 of the check bit data DP0 is modified. To be done. As a result, the read-modify-write circuit 11 outputs new check bit data DP1 (P7 to P1 and P0 ').

Next, the timing circuit 1 forms a write request (RAM-WRITE) to the memory 40 and sends it to the memory 40. At the same time, under the control of the timing circuit 1, the address queue 4 and the multiplexer 5 have the check bit address AP at the head of the address queue 4.
(X'nppp0) is sent to the memory 40, and the multiplexer 8 sends new check bit data DP1 (P7 to P1 and P0 ') output from the read modify write circuit 11 to the memory 40. As a result, the check bit data DP1 is written to the check bit address AP in the memory 40.

As described above, the memory cycle for writing the check bit data (read modify write cycle)
Ends. At the same time, the timing circuit 1 invalidates the check bit address AP and the check bit DPn that were at the head of the address queue 4 and the check bit queue 7 until that time. That is, the check bit address and the check bit stored in the address queue 4 and the check bit queue 7 are sent to the unit circuit of the next stage, respectively.

Next, the read operation in the memory device 100 will be described with reference to FIGS. FIG. 6 shows a read operation in the storage device 100, which includes data D
FIG. 11 is a diagram showing a read operation after the writing of the check bit P0 ′ corresponding to 0 to the memory 40 is completed.

The CPU 20 sends a read request (CPU-READ) for the memory 40 and the address A0 (X'n0000) to the memory control circuit 30. When there is a read request for the memory 40 from the CPU 20, the timing circuit 1 executes the read request (read cycle) because it does not send a busy signal. That is,
Forming various control signals necessary for reading data,
The read circuit 35 is caused to read data, and the error processing circuit 36 is caused to perform error processing.

The timing circuit 1 forms a read request (RAM-READ) to the memory 40 and sends it to the memory 40. At the same time, by controlling the timing circuit 1,
The multiplexer 5 sends the address A0 to the memory 40. As a result, in the next cycle, the data D0 stored in the address A0 (X'n0000) is read from the memory 40. This data D0 is fetched by the error check circuit 10 under the control of the timing circuit 1.

On the other hand, under the control of the timing circuit 1, the address conversion circuit 3 to which the fetched address A0 is input.
Generates the check bit address AP (X'nppp0) in which the check bit DPn (P0 ') corresponding to the data D0 to be read is stored. Then, the timing circuit 1 causes the address comparison circuit 2 to compare the check bit address AP (X'nppp0) generated by the address conversion circuit 3 and each of the check bit addresses stored in the address queue 4. The address comparison circuit 2
Each bit of each unit circuit of the address queue 4 composed of a FIFO buffer is configured to be compared with each bit of the check bit address AP generated by the address conversion circuit 3. As a result, the comparison ends almost at the same time as the input of the check bit address AP from the address conversion circuit 3, so that the read cycle will not be delayed even if this comparison is performed.

In this case, since the check bit P0 'corresponding to the data D0 has already been written in the memory 40, the check bit address AP (X'nppp).
0) does not exist in the address queue 4. Therefore, the result of comparison becomes a mismatch, and a mismatch signal is sent to the timing circuit 1. The above is performed in the same cycle as the transmission of the address A0 to the memory 40.

The timing circuit 1 which receives the mismatch signal,
The read circuit 35 is caused to read the check bit P0 ′ stored in the memory 40. The timing circuit 1 forms a read request (RAM-READ) to the memory 40 again and sends it to the memory 40 in one cycle after temporarily stopping the sending of the read request (RAM-READ). At the same time, under the control of the timing circuit 1, the address conversion circuit 3 again causes the check bit address AP (X '
nppp0), and the multiplexer 5 sends this to the memory 40. As a result, in the next cycle, the check bit address AP (X'nppp
Check bit data DP1 (P
7 to P1 and P0 ') are read. A predetermined check bit DPn in the check bit data DP1
Under the control of the timing circuit 1, (P0 ′) is selectively output by the multiplexer 9 and input to the error check circuit 11. At this time, address A0 (X'n000
Since the value of the least significant bit of 0) is “0”, the least significant bit P0 ′ of the check bit data DP1 is selected.

Under the control of the timing circuit 1, the error check circuit 11 receives the data D0 and the check bit DPn.
(P0 ′) is used to perform an error check on the data D0. If there is no abnormality in the read data D0 as a result of the error check, the timing circuit 1
The data D0 is sent to the PU 20, and at the same time the reading end (CPU-ACK) is sent. Thus, the memory cycle (read cycle) for reading data is completed. As a result, the memory control circuit 30 and the memory 4
0 waits for a memory request from the CPU 20.
If the data D0 is abnormal, the timing circuit 1
An error response is returned to the PU 20 instead of the end of the data D0 and reading.

Next, the read operation in the memory device 100 will be described with reference to FIGS. FIG. 7 shows a read operation in the storage device 100, which includes data D
FIG. 9 is a diagram showing a read operation before the end of writing the check bit P0 ′ corresponding to 0 to the memory 40. Similarly to the case of FIG. 6, the CPU 20 requests the read request (C
PU-READ) and address A0 (X'n0000) are transmitted, and in response thereto, the timing circuit 1 executes the read request (read cycle). That is, the timing circuit 1 requests the memory 40 to read (RAM-REA
D) and the fetched address A0 are sent to the memory 40, and in the next cycle, the data D0 stored at the address A0 (X'n0000) is read from the memory 40 and fetched by the error check circuit 10.

On the other hand, under the control of the timing circuit 1, FIG.
The address conversion circuit 3 generates the check bit address AP (X'nppp0), and the address comparison circuit 2 compares the check bit address AP (X'nppp0) with each of the check bit addresses stored in the address queue 4. .

In this case, contrary to the case of FIG. 6, data D
Since the writing of the check bit P0 ′ corresponding to 0 to the memory 40 is not completed, the check bit address AP (X′nppp0) exists in the address queue 4.
Therefore, the comparison result is in agreement, and the agreement signal is sent to the timing circuit 1. The above is performed in the same cycle as the transmission of the address A0 to the memory 40.

The timing circuit 1 receiving the coincidence signal outputs the check bit P0 'stored in the check bit queue 7 in the next cycle. Data D
In parallel with the reading of 0, under the control of the timing circuit 1, the check bit queue 7 is a check bit stored therein, which corresponds to the check bit DPn corresponding to the address matched in the comparison in the address comparison circuit 2. Output (P0 '). The check bit DPn is input to the multiplexer 9, selectively output by the multiplexer 9 under the control of the timing circuit 1, and input to the error check circuit 11.

Thereafter, similarly to FIG. 6, under the control of the timing circuit 1, an error check is performed on the data D0 using the data D0 and the check bit DPn (P0 ') in the error check circuit 11. Be seen.
Then, the timing circuit 1 sends to the CPU 20 the data D0 and the read end (CPU-ACK) when the data D0 has no abnormality, and returns the error response when the data D0 has abnormality. Thus, the memory cycle (read cycle) for reading data is completed. As a result, the memory control circuit 30 and the memory 4
0 waits for a memory request from the CPU 20.

As can be seen from the comparison between FIG. 6 and FIG.
The read operation in the check bit in the memory 40
It does not need to read from, so it finishes very fast.
Therefore, the performance of the memory 40 viewed from the CPU 20 can be improved accordingly. Further, in the storage device 100 in which written data is often read out after several cycles,
By increasing the number of stages of the unit circuits of the check bit write queue circuit 34 to some extent, almost all the read operations are the read operations in FIG.

Next, the password circuit 37 will be described with reference to FIG.
This will be described with reference to FIGS. 4 and 8. As mentioned above, memory 4
Since 0 is a flash memory, its reading can be freely performed, but writing requires setting (cancellation) of a password in a predetermined sequence. Therefore, the password circuit 37 sets the password according to the sequence in the write cycle to the memory 40 and the check bit write cycle.

In the write cycle of the data D0 to the memory 40, as shown in FIG. 8A, the read / write control circuit 31 (timing circuit 1) performs the following sequences S1 to S3 on the password circuit 37. Let

The password circuit 37 is the timing circuit 1
Under the control of, the address 0X05555 and the data 0Xaa are output at a predetermined timing. The multiplexer 5 and the multiplexer 8 output the address 0X05555 and the data 0Xaa to the memory 40 under the control of the timing circuit 1. At this time, the timing circuit 1 sends a write request (RAM-WRITE) to the memory 40. As a result, the data 0Xaa is written to the address 0X05555 of the memory 40 (S1).

Similarly, the address 0X02aaa and the data 0X55 output by the password circuit 37 are used for the memory 40.
The data 0X55 is written to the address 0X02aaa (S2).
Similarly, the address 0X output by the password circuit 37
Address 0X of memory 40 by 05555 and data 0Xaa
Data 0Xaa is written to 05555 (S3).

As described above, the setting of the password for the memory 40 is completed, and the writing becomes possible. In order to perform the sequences S1 to S3, the password circuit 37
Are address 0X05555, data 0Xaa, address 0X
02aaa, data 0X55, and the order of this transmission are stored. That is, the password circuit 37 uses this sequence S1.
To S3 are stored, and the sequences S1 to S3 are automatically performed under the control of the timing circuit 1 in the write cycle.

The data write circuit 32 writes the data D0 to the address 0Xn0000 (A0) of the memory 40 as described above (S4). In the above-mentioned check bit write cycle of the check bit data DP1 to the memory 40, the read / write control circuit 31 causes the password circuit 37 to perform the following sequences S7 to S9, as shown in FIG. 8B.

The read circuit 35 operates as described above.
The check bit data DP0 is read from the address 0Xnppp0 (AP) of the memory 40 (S5). Since this is a read operation, there is no need to set a password.

The check bit write circuit 33 reads the check bit data DP0 as described above.
The new check bit data DP1
Are formed (S6).

The password circuit 37 outputs the address 0X05555 and the data 0Xaa in the same manner as described above. Then, in the same manner as described above, the address 0X05555 of the memory 40 is displayed.
Data 0Xaa is written in (S7).

Similarly, according to the address 0X02aaa and the data 0X55 output from the password circuit 37, the memory 40
The data 0X55 is written to the address 0X02aaa of the (S8).
Similarly, the address 0X output by the password circuit 37
Address 0X of memory 40 by 05555 and data 0Xaa
Data 0Xaa is written to 05555 (S9).

As described above, the setting of the password for the memory 40 is completed, and the writing becomes possible. The password circuit 37 stores these sequences S7 to S9,
In the check bit write cycle, the sequences S7 to S9 are automatically performed under the control of the timing circuit 1.

The check bit write circuit 33 writes the new check bit data DP1 to the address 0Xnppp0 of the memory 40 as described above (S10). As a result, even if the memory 40 is a flash memory,
The CPU 20 can perform the write cycle without being aware of this. Also, the password setting is
This can be done at high speed because it is done by the password circuit 37, not by the software of the CPU 20.

[0085]

As described above, according to the present invention,
In a storage device having a data error check function, by providing hardware that temporarily holds a check bit and a check bit address, writing / reading is performed while maintaining a mutual correspondence relationship between the check bit and the data. Therefore, it is possible to improve the execution speed of the memory write / read, and it is possible to eliminate the need to perform the check bit write operation consecutively to the data write operation, so that the check bit write operation is completed. The next memory request from the CPU can be accepted without waiting, and C
Since the write operation of the check bit can be executed while the memory request is not issued from the PU, it is possible to prevent the check bit write operation from interfering with the execution of the memory request from the CPU. It is possible to improve the memory performance seen from the CPU while preventing the deterioration of the memory utilization efficiency by adopting the method of storing the check bit and the check bit in different addresses.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a storage device.

FIG. 3 is an explanatory diagram of a memory.

FIG. 4 is an explanatory diagram of a memory control circuit.

FIG. 5 is an explanatory diagram of a write operation.

FIG. 6 is an explanatory diagram of a read operation.

FIG. 7 is an explanatory diagram of a read operation.

FIG. 8 is an explanatory diagram of password control.

[Explanation of symbols]

 1 Timing Circuit 2 Address Comparison Circuit 3 Address Conversion Circuit 4 Address Queue 5, 8, 9 Multiplexer 6 Check Bit Generation Circuit 7 Check Bit Queue 10 Error Check Circuit 11 Read Modify Write Circuit 20 CPU 30 Memory Control Circuit 31 Read / Write Control Circuit 32 Data write circuit 33 Check bit write circuit 34 Check bit write queue circuit 35 Read circuit 36 Error processing circuit 37 Password circuit 40 Memory 100 Storage device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Saito 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (7)

[Claims] 1. A memory for storing data and a check bit corresponding to the memory at different addresses, and a check bit corresponding to the memory is generated based on the data sent from the CPU. A check bit write circuit that generates a check bit address that stores the generated check bit based on a corresponding address, and writes a check bit to the check bit address, and a check bit and a check bit address that the check bit write circuit generates And a check bit write queue circuit that stores the check bit write queue circuit, the check bit write queue circuit storing the check bit write queue circuit in a period in which there is no read request or write request from the CPU to the memory. A storage device for writing a check bit corresponding to the check bit to a check bit address stored in the check bit write queue circuit corresponding thereto. 2. The check bit write circuit generates a check bit corresponding to the data sent from the CPU based on the data sent from the CPU, and an address corresponding to the data sent from the CPU. And an address conversion circuit that generates a check bit address that writes the check bit generated corresponding to the data, and the check bit write queue circuit stores the check bit generated by the check bit generation circuit. The storage device according to claim 1, comprising a bit queue and an address queue that stores a check bit address generated by the address conversion circuit. 3. The check bit write queue circuit comprises a FIFO buffer having a predetermined number of stages, and the check bit write circuit writes the check bits in the order stored in the check bit write queue circuit. The storage device according to claim 1 or 2. 4. The storage device further comprises a data write circuit for writing data sent from the CPU to the memory, and the check bit write queue circuit is vacant when there is a write request from the CPU to the memory. When there is, the data write circuit writes the data sent from the CPU to an address corresponding to the data in the memory, and the check bit write circuit writes the check bit and the address generated based on the data. 4. The storage device according to claim 1, wherein a check bit address generated based on the check bit write queue circuit is stored in the check bit write queue circuit. 5. The memory is a memory in which check bits are stored as a set of check bits in which a plurality of check bits corresponding to a plurality of data are collected and have the same size as one data. A bit writing circuit reads a set of check bits stored in the check bit address stored in the check bit write queue circuit from the memory, and sets a check bit at a predetermined position in the set of check bits to the check bit address. The check bit is written by exchanging the check bit stored in the corresponding check bit write queue circuit and writing the set of the exchanged check bits to the check bit address of the memory. In claim 1 Placing the storage device. 6. The error processing for the storage device, further comprising: a read circuit for reading out data and check bits written in the memory; and an error check for the data using the data and check bits corresponding to the data. A circuit, wherein the error processing circuit is data read by the read circuit and check bits corresponding to the data, the check bit read by the read circuit or the check bit stored by the check bit write queue circuit. The storage device according to claim 1, wherein an error check is performed on the data by using and. 7. The storage device further controls reading from and writing to the memory, and a CPU
And a read / write control circuit for comparing the check bit address generated by the check bit write circuit based on the address with the address stored in the check bit write queue circuit when there is a read request to the memory from the check bit write circuit. If the result of the comparison does not match, the read circuit reads the data stored in the address from the memory, and the check bit stored in the check bit address generated by the check bit write circuit based on the address. Read out, the error check circuit performs an error check using the read data and check bits, and if the result of the comparison matches, the read circuit reads the data stored at the address from the memory. Read from, The check bit write circuit outputs a check bit corresponding to the data stored in the check bit write queue circuit, and the error check circuit uses the read data and the output check bit to make an error. The storage device according to claim 6, wherein a check is performed.