GB2260836A - Bus Interface - Google Patents

Abstract

A circuit 30 interfaces between a bus of a system and a peripheral and comprises a port for connection to the system bus 10, connection means 17 for connection to a peripheral, data registers 11 for transferring data to and from the port and the connection means, an address register 12 for addressing memory locations in the system and the peripheral and for receiving addresses from the system and the peripheral, an address generator 13 for generating addresses for reading of data from the system and the peripheral and a transfer counter 14. A bus controller circuit 25, discrete from the interface circuit, is coupled to the interface and to the system bus, for controlling the timing of transfers between the system bus and the port. Data transfers can be performed in blocks or pages in accordance with the capacity of the data registers and the number of transaction per block are counted by the transfer counter 14. The arrangement may be used in any communication device such as "Ethernet" or "Token Ring" controllers and any DMA controller, disc controller etc. <IMAGE>

Description

SYSTEM PORT INTERFACE Background of the Invention This invention relates to an interface for communication between the bus of a processor system and a peripheral bus or line such as a fibre distributed data network.

Summary of the Prior Art Existing bus interface units such as DMA controllers, bus arbiters, memory controllers and the like are adapted to all the characteristics of the system in which they have to function, i.e. address bus width, data bus width, address and data bus attributes (multiplexed or not multiplexed), mechanism of gaining ownership of the bus in the case of a multi-master bus, mechanism of gaining the right to access a multi-access memory in the case of implementation of this type of memory around a regular type of RAM and so forth.

There are many different approaches to bus algorithms. Each one suits the application and environment in which it is to be used.

Figure 1 shows an example of an existing bus interface unit. It comprises an external address/data bus 10, data registers 11, and an address register 12, an address generator 13, a transfer counter 14, a bus controller 15 and control lines 16. The interface unit interfaces with â peripheral bus or line 17.

The data registers 11 store the data to be transferred in a current bus transaction. The address generator 13 and address output register 12 generate and store the address for the next bus transfer. The transfer counter 14 counts the number of transactions done on the bus for the current block transfer and the bus controller 15 is responsible for the bus protocol management. An interface unit such as is shown in Figure 1 suffers from a lack of flexibility as it is strictly adapted to the user implementation on one hand and on the other hand does not achieve optimum bus performance in each specific system, because it must fit the minimum common denominator of all possible applications.

It would be desirable to provide a tool to any user to allow him the implementation of proprietary interfaces without carrying any loss of performance.

Summary of the Invention According to the invention there is provided a bus interface comprising: an interface circuit for interfacing between a bus of a system and a peripheral comprising: a port for connection to the system bus; connection means for connection to the peripheral; data registers coupled for transfer of data to and from the port and the connection means; an address register coupled for addressing memory locations in the system and the peripheral and for receiving addresses from the system and the peripheral; an address generator for generating addresses for reading of data from the system and the peripheral and a transfer counter for counting transfers between the port and the connection means; and a bus controller circuit, discrete from said interface circuit, coupled to the interface and having means for coupling to the system bus, for controlling the timing of transfers between the system bus and the port.

Brief Description of the Drawings Figure 1 shows a bus interface unit in accordance with prior art.

Figure 2 shows a system interface in accordance with a first preferred embodiment of the invention.

Figure 3 shows the interface of Figure 2 in a system.

Figure 4 is a timing diagram describing the operation of the interface of Figure 2.

Figure 5 shows further detail of the system interface of Figure 2.

Figure 6 is a block diagram of two-port interface in accordance with a second embodiment of the invention.

Figure 7 is a block diagram of the system of Figure 6 with a more extensive system connected to the second port.

Detailed Description of the Preferred Embodiment A preferred embodiment of the invention will now be described by way of example.

Referring to Figure 2, there is shown a system interface 30 having certain elements in common with the interface of Figure 1, which are given the same reference numerals. The interface comprises an external address/data bus 10, data registers 11 coupled to the bus 10, an address register 12 coupled to the bus 10, an address generator 13 coupled to the address register 12, a transfer counter 14 and a peripheral bus or line 17. The interface further comprises a 4-bit register address bus input 20 and four request lines 21 to 24. Connected to the register address input 20 and the request lines 21 to 24 is an external bus controller 25. The request lines are: read/write request line 21; chip select request line 22; same page/next page indicator request line 23 and type of data descriptor request line 24.

As shown in Figure 3, the system interface 30 of Figure 2 is connected to a main controller 41 and internal memory 42 via an internal bus 45. The system interface 30, main controller 41, internal memory 42 and internal bus 45 together form a fibre network system interface (FSI). The FSI is connected to a processor system typically comprising a host processor 31 a system memory 32 and a system bus 33, to which the external address/data bus 10 is connected. The bus controller 25 is also connected to the system bus 33 by means of control lines 34.

The FSI 40 facilitates the transfer of data between a system memory and an fibre network. On the network, the data is transmitted in units of "symbols", two of which are combined together to form a byte. For this purpose, the data to be transmitted in broken down to the level of bytes and the bytes are transmitted consecutively.

The operation of the FSI 40 will first be described through the example of a DMA transfer from the system memory 32 to the interface bus or line 17, at the request of the peripheral device.

A DMA instruction is received by the interface 30 from the peripheral device with an address indicator identifying the block of memory to be transferred. The address generator 13 generates the start address, which is stored in address register 12 and, under control of the external bus controller 25, initiates a DMA transfer from the system memory 32 through the external address/data bus 10 into the data registers 11 and from the data registers 11 to the peripheral bus or line 17. The transfer is performed in blocks or pages in accordance with the capacity of the data registers 11 and the number of transactions per block is counted by the transfer counter 14.

Many other types of transfer can be performed.

The FSI 40 handshakes with the system bus 33 under the control of the external bus controller 25 by means of the request lines 21 to 24, as shown in Figure 4.

In that Figure, there is shown a timing diagram for signals on the next page/same page indicator line 22 (REQ), the chip select line 23 (CS) the register address bus 20 (RAB), the read/write line 21 and the external address/data bus 10.

The register address bus 20 selects the register in the system interface 30 to be accessed, the read/write request line 21 defines the type of access and the chip select signal 23 activates the external bus controller 25. The request lines are valid for each data transfer to be executed. In the example of Figure 4, a read cycle is shown, in which the combination of a transition on request line 22 and read/write line 21 initiates the read cycle. The external bus controller 25 provides an address on register address bus 20 referring to the register to be addressed. An address is output by the system interface 30 on external address/data bus 10. Each subsequent transition on the new page request line 22 causes a page of data to be read from the system memory 32 to the system interface 30 over-the external address/data bus 10.

The internal connection of the interface 30 and other internal blocks of the FSI 40 is shown in Figure 5. The FSI 40 is a master device, i.e. it is an initiator of data transfers between the system memory 32 and the internal memory 42 for temporary data storage.

The data in system memory 32 is arranged in data buffers. The buffer descriptor information (buffer length and buffer start address) is known to the FSI 40 before it starts to transfer data to/from this buffer. This information is stored in the main controller 41 of the FSI.

Two small FIFO's 43 and 44 are used as temporary buffers between the main controller 41 and the system interface 30 for synchronization between the system bus 33 and the internal bus 45.

An example will now be described of data transfer from system memory 32 to internal memory 42. In order to initiate a transfer, the main controller 41 writes the system buffer address into the address generator 13 and the buffer size into the transfer counter 14 of the system interface 30. The system interface 30 then requests the new read cycle from the external bus controller 25 using its request lines 21 to 24.

The external bus controller is responsible for external bus timing and an external bus arbitration. In a response to a request from the system interface 30, the external bus controller 25 requests the external bus for read access. In order to find the address of the external bus access, the external bus controller 25 accesses the address register 12 of the system interface 30. This address register is an output register of the address generator 13 and always holds the system memory address of the required data access. In order to transfer the data from the system memory to FSI 40, the external bus control logic 25 generates all the control signals 34 required by the external bus and also performs the write access to the data register 11 of the system interface 30. The data is therefore transferred from the system memory 32 through the external bus 33 into the data register 11.

The system interface 30 then transfer this data from the data register 11 into the intermediate FIFO 43. The entries of the FIFO 43 are transferred later onto the internal memory 42. During the access to the data register 11 the system interface 30 changes the states of the request lines 21 to 24 to indicate the next request. If there is more data to transfer (transfer counter 14 is not zero) request lines 21 to 24 indicate another read request. The system interface 30 also determines the address of the next data access and compares this address to a previous one. If both of these addresses are in the same memory page, the "same page" request line 23 is asserted. When the last data is written to the data register 11, the request lines 21 to 24 indicate the "idle" state and no more accesses are requested.

The procedure for data transfer from internal memory 42 to system memory 32 is similar to the above. For a data transfer in this direction, the main controller 41 of the FSI writes the data from internal memory into the intermediate FIFO 44. This data is then transferred to into the data register 11 by the system interface 30, is read by the external bus controller to the external bus controller to the external bus 33 and finally is written into the system memory 32.

The arrangement described and claimed may be used in any communication device such as "Ethernet" (trademark) or "TokenRing" controller etc. and in any DMA device such as system DMA controller, disk controller etc. The interface unit 30 with its external data bus 10 register address bus 20 and external bus controller 25 together form a master DMA device which is tightly coupled to an external bus.

In cases where either the system bus bandwidth is not sufficient to meet the fibre network requirements concerning latency or sustained transfer rate or when a local processor is desired in order to enhance the operation of a fibre network adaptor, enhancements to the system interface can be made to provide increased user flexibility at low cost. Such an enhancement is shown in Figure 6. In this figure, local memory 50 is added to the FSI 40 by means of a local bus 52.

Memory control circuitry 53 is connected between the interface unit and the local memory 50.

Receive frames are first received into the local memory 50 and then may be transferred to the system memory 32.

Correspondingly, transmit frames are first transferred from the system memory 32 to the local memory 50 and then transmitted to the network over peripheral bus or line 17.

The enhancement allows this process to take place either automatically (local memory only configuration) or semiautomatically (local memory plus local processor).

A node processor 60 can be connected to the local bus 52 and the local memory port (port B) as shown in Figure 7.

This processor may take care of station management tasks and may perform some pre-processing of received data and some processing on transmit data in order to release the host processor 31 from communication tasks. This freeze the host processor to deal only with "pure" data files and/or complete messages transferred from one station to another, where each file may have consisted of one or more frames on the network.

Claims (5)

1. A bus interface comprising: an interface circuit for interfacing between a bus of a system and a peripheral comprising: a port for connection to the system bus, connection means for connection to the peripheral, data registers coupled for transfer of data to and from the port and the connection means, an address register coupled for addressing memory locations in the system and the peripheral and for receiving addresses from the system and the peripheral, an address generator for generating addresses for reading of data from the system and the peripheral and a transfer counter for counting transfers between the port and the connection means, a bus controller circuit, discrete from said interface circuit, coupled to the interface and having means for coupling to the system bus, for controlling the timing of transfers between the system bus and the port.

2. A bus interface according to claim 1, further comprising a read/write request line from the interface circuit to the bus controller.

3. A bus interface according to claim 1, further comprising a same page/next page request line from the interface circuit to the bus controller.

4. A bus interface according to claim 1, further comprising a type of data descriptor request line from the interface circuit to the bus controller.

5. A bus interface according to claim 1 wherein the bus controller circuit is arranged to control arbitration on the bus.