JPS62231367A - Dma data transfer system - Google Patents

Abstract

PURPOSE:To permit a system bus to be used in process of a DMA data transfer, by providing a DMA private bus between a memory and an interface, and performing the transfer of data trough the DMA private bus between the memory and the interface. CONSTITUTION:A CPU2, a memory M3, and an interface I/F4 are coupled by a system bus 1, and a private bus 5 is provided between the M3 and the I/F4 when a data transfer is performed between the M3 and the I/F4. A part of the M3 is constituted so as to be controlled so that it can be cross-connected to the bus 1 and the bus 5 by a gate. In process of the transfer of the DMA data to the M3 through the DMA private bus 5, the use of the bus 1 by the CPU2 is permitted. In this way, the processing efficiency of the CPU2, and therefore, a system efficiency can be improved.

Description

Detailed Description of the Invention A. Industrial Field of Application The present invention relates to a DMA data transfer method between an interface and a memory in a computer system. By providing a DMA dedicated bus between the interfaces and allowing data to be exchanged between the memory and the interface through the DMA dedicated bus, the system bus can be used during DMA data transfer.

C1 Prior Art] In computer systems Q, D is conventionally used to transfer large amounts of data between the system memory and interface
It is performed by MA Manshiki. In FIG. 4, a system bus 1 connects an 0PU2, a memory 3, and an interface 4, and performs a DMA operation (this transfers the memory location address and data size to the interface 4).
Writing to the register of tr2 and activating the DMA, the interface 4 prohibits the OPU 2 IC from using the system bus 1, and sends and receives data in an amount equal to the data size from the memory location specified in the memory 3.

This data exchange is performed through the data bus of the system bus 1.

Problems to be solved by the D0 invention In the conventional DMA data transfer system, interface 4
aPU2; controls the bus by giving addresses and data to memory 3, restricting access to the 2 bus. Therefore, during DMA data transfer, C! There is a problem in that the bus access rate of PU2 lowers the operating efficiency of 0PU2 and thus the system processing efficiency.

Means and operation for solving the E0 problem The present invention has been made in view of the above problems. The configuration is configured to switch and control the connection between the bus and the DMA dedicated bus, and data is exchanged between the interface and the memory via the DMA dedicated bus. Instead, the system bus can be occupied by the OPU even during DMA data transfer.

F. Embodiment FIG. 1 is a system configuration diagram showing an embodiment of the present invention. The difference between this figure and FIG. 4 is that a dedicated DMA bus 5 is provided between the memory 3 and the interface 4, and in addition to the conventional DMA data transfer via the system bus 1 for data transfer between the memory 3 and the interface 4, DMA The DMA data transfer is performed through the dedicated bus 5.
During data transfer through dedicated bus 5, this is arranged to allow 0PU2# to use the system bus.

The specific structure of this system configuration is shown in WJ2 figure and 3.
The details will be explained with reference to the drawings.

FIG. 2 shows the configuration of the memory 3. 4 memory cells 11
1 to 114, memory cell 11. 113 are coupled to the address bus IA, data bus ID, and bank address decoder 12 of the system bus 1 to enable data transfer via the system bus 1. Memory cell 114
is coupled to the address bus IA% data bus lDj via gates 13 and 14, and to the address bus 5A and data bus 5D of the DMA dedicated bus 5 via gates 15 and 16. Gate 1 by gate control signal (GATIn-l) of dedicated bus 5
When one of the gates 3, 14 and 15, 16 is opened, they are connected to either the system bus 1 or the DMA dedicated bus 5.

FIG. 3 shows the configuration of the interface 4. For system bus 1, address register 4A, word count register 4B, and xD7'irR data request register 4C.
The contents of the DMA data transfer are written from the system bus 1 to each register 4A to 40 by 0PU2.

In such a configuration, during normal data exchange, the address recorder 12 creates select signals for each memory cell 111 to 114 from the address data from the system bus 1.
Memory cell 1 depending on which bank's memory area
1. ~1] Issue an access request to 4. Memory cell 11. ~11. The address is determined from the select @ number and address data, and if the control signal is RD, the data at the address is sent to the system bus 1, and if it is WR, the data is fetched from the system bus 1 and stored.

Next, when transmitting and receiving data between the memory cell 114 and the interface 4 using the DMA dedicated bus 5, the interface 4 creates an address signal for the DMA dedicated bus of the memory location from the value of the address register 4A, and inputs the address signal to the word counter register. RD/ of register 40 up to 4B pieces
'According to the request of WR, from the memo request to the end of DMA, gates 13 and 1 are
．． 4 and open gates 15 and 16. Therefore, D.M.
During data transfer via the A-only bus 5, the system bus 1 can be occupied by aptr2 and the remaining memory cells 11. ~11. It enables data transfer and control between devices and peripheral devices using other interfaces.

Effects of the G1 Invention As described above, according to the present invention, a dedicated DMA bus is provided between the memory and the interface, and DMA processing using the bus is possible.
To enable data transfer, during DMA data transfer (this system bus% OPU can be used, OPH
This has the effect of improving processing efficiency and system efficiency.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram showing one embodiment of the present invention;
This figure is a block diagram of the memory in FIG. 1, and FIG. 4 is a block diagram of a conventional computer system. 1... System bus, 2... OPU, 3... Memory, 4... Interface, 5... DMA dedicated lotus, 11, 1114... Memory cell, 12... Address data ,■3114115 ,16...Gate,
4 people: Address register, 4B: Word count register, 40: RD/VRDMA request register. Fig. 1 System bus 1 - System bus 2 - CPU 3 - 11 11 4 - - Δ Ngu Moose 5 - - DMA Turtle gus'

Claims (1)

[Claims] In data transfer between a memory and an interface connected by a system bus, a DMA dedicated bus is provided between the memory and the interface, and at least a portion of the memory is configured to control switching connection between the system bus and the DMA dedicated bus using a gate. DMA data transfer method, characterized in that data is exchanged between the interface and the memory through the DMA dedicated bus.