JPS56118128A - Interruption controlling system for peripheral control chip of microcomputer - Google Patents

Interruption controlling system for peripheral control chip of microcomputer

Info

Publication number
JPS56118128A
JPS56118128A JP2054880A JP2054880A JPS56118128A JP S56118128 A JPS56118128 A JP S56118128A JP 2054880 A JP2054880 A JP 2054880A JP 2054880 A JP2054880 A JP 2054880A JP S56118128 A JPS56118128 A JP S56118128A
Authority
JP
Japan
Prior art keywords
interruption
bundle
microcomputer
peripheral control
control chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2054880A
Other languages
Japanese (ja)
Other versions
JPH0154735B2 (en
Inventor
Katsuhiko Ueda
Takashi Sakao
Koichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2054880A priority Critical patent/JPS56118128A/en
Publication of JPS56118128A publication Critical patent/JPS56118128A/en
Publication of JPH0154735B2 publication Critical patent/JPH0154735B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To remarkably reduce the troublesomeness of procedure and the time required for it, by making the permission and dispermission of interruption to all the functional blocks in the chip at a bundle and enabling the retrieval of interruption request at a bundle. CONSTITUTION:In a peripheral chip, status control registers 1-7, interruption permission register 8 and interruPtion request register 9 are provided. The specific address is assigned to the registers with the address decoder 10, and each bit in the registers is operated and retrieved at a bundle from the computer side through the data bus 11 and the internal data bus 12.
JP2054880A 1980-02-22 1980-02-22 Interruption controlling system for peripheral control chip of microcomputer Granted JPS56118128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2054880A JPS56118128A (en) 1980-02-22 1980-02-22 Interruption controlling system for peripheral control chip of microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2054880A JPS56118128A (en) 1980-02-22 1980-02-22 Interruption controlling system for peripheral control chip of microcomputer

Publications (2)

Publication Number Publication Date
JPS56118128A true JPS56118128A (en) 1981-09-17
JPH0154735B2 JPH0154735B2 (en) 1989-11-21

Family

ID=12030197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2054880A Granted JPS56118128A (en) 1980-02-22 1980-02-22 Interruption controlling system for peripheral control chip of microcomputer

Country Status (1)

Country Link
JP (1) JPS56118128A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61201339A (en) * 1985-02-28 1986-09-06 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Interrupt control method and apparatus
JPS6224329A (en) * 1985-07-23 1987-02-02 Mitsubishi Electric Corp State signal detector
JPS63159938A (en) * 1986-12-24 1988-07-02 Mitsubishi Electric Corp Data processor
JPS63271654A (en) * 1987-04-30 1988-11-09 Yokogawa Medical Syst Ltd Multiprocessor system
JPH0227450A (en) * 1988-06-30 1990-01-30 Internatl Business Mach Corp <Ibm> Collection method and system for erroneous interrupt data

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61201339A (en) * 1985-02-28 1986-09-06 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Interrupt control method and apparatus
JPS6224329A (en) * 1985-07-23 1987-02-02 Mitsubishi Electric Corp State signal detector
JPS63159938A (en) * 1986-12-24 1988-07-02 Mitsubishi Electric Corp Data processor
JPS63271654A (en) * 1987-04-30 1988-11-09 Yokogawa Medical Syst Ltd Multiprocessor system
JPH0227450A (en) * 1988-06-30 1990-01-30 Internatl Business Mach Corp <Ibm> Collection method and system for erroneous interrupt data
JPH0465411B2 (en) * 1988-06-30 1992-10-20 Intaanashonaru Bijinesu Mashiinzu Corp

Also Published As

Publication number Publication date
JPH0154735B2 (en) 1989-11-21

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