JPS57113166A - Data processor - Google Patents

Data processor

Info

Publication number
JPS57113166A
JPS57113166A JP18827980A JP18827980A JPS57113166A JP S57113166 A JPS57113166 A JP S57113166A JP 18827980 A JP18827980 A JP 18827980A JP 18827980 A JP18827980 A JP 18827980A JP S57113166 A JPS57113166 A JP S57113166A
Authority
JP
Japan
Prior art keywords
control signal
constitution
memory
data processor
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18827980A
Other languages
Japanese (ja)
Inventor
Hiroshi Tamura
Shoji Nakatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18827980A priority Critical patent/JPS57113166A/en
Publication of JPS57113166A publication Critical patent/JPS57113166A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To shorten the time of parallel accessing and to improve processing efficiency, by forming a write control signal for the memory modules of multiple-bank constitution including a bit which instructs writing or write inhibition corresponding to each module. CONSTITUTION:A memory M which has memory modules MDL of multiple-bank BNK constitution is accessed through a memory access controller MCU by a data processor which includes a CPU, a channel device CHP, and a vector processor VPU. Data buses BUS are connected between the controller MCU and data processor, and a write control signal to modules MDL is generated including a byte mark BYM consisting of specified bits, which correspond to a module number for parallel access, in addition to bits (a) and (b) which constitute a store control signal ST for independent access, thereby improving processing efficiency.
JP18827980A 1980-12-29 1980-12-29 Data processor Pending JPS57113166A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18827980A JPS57113166A (en) 1980-12-29 1980-12-29 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18827980A JPS57113166A (en) 1980-12-29 1980-12-29 Data processor

Publications (1)

Publication Number Publication Date
JPS57113166A true JPS57113166A (en) 1982-07-14

Family

ID=16220866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18827980A Pending JPS57113166A (en) 1980-12-29 1980-12-29 Data processor

Country Status (1)

Country Link
JP (1) JPS57113166A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0442496A2 (en) * 1990-02-15 1991-08-21 Nec Corporation Memory access control device having bank access checking circuits smaller in number than the memory modules
US5214769A (en) * 1987-12-24 1993-05-25 Fujitsu Limited Multiprocessor control system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51139218A (en) * 1975-05-28 1976-12-01 Hitachi Ltd Memory
JPS5368922A (en) * 1976-11-29 1978-06-19 Rca Corp Parallel access memory system
JPS54102928A (en) * 1978-01-31 1979-08-13 Fujitsu Ltd Data reading out control system
JPS54122039A (en) * 1978-03-15 1979-09-21 Toshiba Corp Electronic computer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51139218A (en) * 1975-05-28 1976-12-01 Hitachi Ltd Memory
JPS5368922A (en) * 1976-11-29 1978-06-19 Rca Corp Parallel access memory system
JPS54102928A (en) * 1978-01-31 1979-08-13 Fujitsu Ltd Data reading out control system
JPS54122039A (en) * 1978-03-15 1979-09-21 Toshiba Corp Electronic computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214769A (en) * 1987-12-24 1993-05-25 Fujitsu Limited Multiprocessor control system
EP0442496A2 (en) * 1990-02-15 1991-08-21 Nec Corporation Memory access control device having bank access checking circuits smaller in number than the memory modules

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