JPS5475938A - Data processor of multiplex artificial memory system - Google Patents

Data processor of multiplex artificial memory system

Info

Publication number
JPS5475938A
JPS5475938A JP14340777A JP14340777A JPS5475938A JP S5475938 A JPS5475938 A JP S5475938A JP 14340777 A JP14340777 A JP 14340777A JP 14340777 A JP14340777 A JP 14340777A JP S5475938 A JPS5475938 A JP S5475938A
Authority
JP
Japan
Prior art keywords
region
tlb
artificial space
entry
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14340777A
Other languages
Japanese (ja)
Inventor
Takashi Sakai
Saburo Kaneda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14340777A priority Critical patent/JPS5475938A/en
Publication of JPS5475938A publication Critical patent/JPS5475938A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To aviod the collision of artificial space and to simple earse the content of arbitrary artificial space from TLB, by constituting the processor that each entry group of the conversion index buffer set LTB is in exclusive use of the artificial space assigned.
CONSTITUTION: In indexing the conversion index buffer set TLB, either one of the region 0 to n of the high speed memory 11-0 is selected one of the entries within the region selected with a part of the logical address is selected, the ligical address and real page address are read out from the selected entry, if the both are in agreement 12-0, the gate 13-0 is opened and the real page address is outputted to external. Further, the same iperation is made to the high speed memory 11-1. Next, if the information relating to the artificial space 2 is erased from TLB for example, the memory 11-0 and 11-1 region 2 are selected, and the effective bit of the total entry at the region 2 is turned off.
COPYRIGHT: (C)1979,JPO&Japio
JP14340777A 1977-11-30 1977-11-30 Data processor of multiplex artificial memory system Pending JPS5475938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14340777A JPS5475938A (en) 1977-11-30 1977-11-30 Data processor of multiplex artificial memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14340777A JPS5475938A (en) 1977-11-30 1977-11-30 Data processor of multiplex artificial memory system

Publications (1)

Publication Number Publication Date
JPS5475938A true JPS5475938A (en) 1979-06-18

Family

ID=15338044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14340777A Pending JPS5475938A (en) 1977-11-30 1977-11-30 Data processor of multiplex artificial memory system

Country Status (1)

Country Link
JP (1) JPS5475938A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603081A (en) * 1983-06-18 1985-01-09 Dainippon Printing Co Ltd Ic card
JPS63254544A (en) * 1987-04-10 1988-10-21 Nippon Telegr & Teleph Corp <Ntt> Control system for address conversion
JP2000259498A (en) * 1999-03-10 2000-09-22 Internatl Business Mach Corp <Ibm> Instruction cache for multi-thread processor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603081A (en) * 1983-06-18 1985-01-09 Dainippon Printing Co Ltd Ic card
JPH0554158B2 (en) * 1983-06-18 1993-08-11 Dainippon Printing Co Ltd
JPS63254544A (en) * 1987-04-10 1988-10-21 Nippon Telegr & Teleph Corp <Ntt> Control system for address conversion
JP2000259498A (en) * 1999-03-10 2000-09-22 Internatl Business Mach Corp <Ibm> Instruction cache for multi-thread processor

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