JPS5532159A - Memory system - Google Patents

Memory system

Info

Publication number
JPS5532159A
JPS5532159A JP10525078A JP10525078A JPS5532159A JP S5532159 A JPS5532159 A JP S5532159A JP 10525078 A JP10525078 A JP 10525078A JP 10525078 A JP10525078 A JP 10525078A JP S5532159 A JPS5532159 A JP S5532159A
Authority
JP
Japan
Prior art keywords
register
address
memory
content
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10525078A
Other languages
Japanese (ja)
Inventor
Takeshi Murata
Hiroyuki Koarai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10525078A priority Critical patent/JPS5532159A/en
Publication of JPS5532159A publication Critical patent/JPS5532159A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to constitute the memory system incorporating the buffer memory in one chip, by setting the column address to the column address register at present address and performing access.
CONSTITUTION: The system provides the memory cell 2 of m x n bits, row address register 3 accessing the cell 2, and the data latch 5 corresponding to the row accessed based on the content of the register 3. After the content of the register 3 is set to the memory unit, the content of the column address register 4 is set, and the row address related to the address information accessed and the present row address related to the address information to be addressed are compared at the comparator. Further, when coincidence output is made, by setting only the column address to the register 4 at present access and performing access, through the use of existing memory unit, the memory system incorporating the buffer memory in one chip can be constituted.
COPYRIGHT: (C)1980,JPO&Japio
JP10525078A 1978-08-29 1978-08-29 Memory system Pending JPS5532159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10525078A JPS5532159A (en) 1978-08-29 1978-08-29 Memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10525078A JPS5532159A (en) 1978-08-29 1978-08-29 Memory system

Publications (1)

Publication Number Publication Date
JPS5532159A true JPS5532159A (en) 1980-03-06

Family

ID=14402399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10525078A Pending JPS5532159A (en) 1978-08-29 1978-08-29 Memory system

Country Status (1)

Country Link
JP (1) JPS5532159A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60555A (en) * 1982-11-15 1985-01-05 デ−タ−・ゼネラル・コ−ポレ−シヨン General-purpose memory
JPH0469750A (en) * 1990-07-11 1992-03-04 Nec Corp Memory control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60555A (en) * 1982-11-15 1985-01-05 デ−タ−・ゼネラル・コ−ポレ−シヨン General-purpose memory
JPH0469750A (en) * 1990-07-11 1992-03-04 Nec Corp Memory control system

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