JPS5616982A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS5616982A
JPS5616982A JP9141879A JP9141879A JPS5616982A JP S5616982 A JPS5616982 A JP S5616982A JP 9141879 A JP9141879 A JP 9141879A JP 9141879 A JP9141879 A JP 9141879A JP S5616982 A JPS5616982 A JP S5616982A
Authority
JP
Japan
Prior art keywords
address
unit
buffer
accessing
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9141879A
Other languages
Japanese (ja)
Other versions
JPS5922315B2 (en
Inventor
Hirosada Tone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54091418A priority Critical patent/JPS5922315B2/en
Publication of JPS5616982A publication Critical patent/JPS5616982A/en
Publication of JPS5922315B2 publication Critical patent/JPS5922315B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To increase the capacity per one associative and to make large the memory unit, by accessing the logical address buffer memoy unit.
CONSTITUTION: By using the in-page address consisting of bits 20W28 of the effective address register 1 together with the lower rank address of the page address consisting of the bits 8W19 of the register 1, accessing is made to the buffer memory unit having the tap 6 and the data 7. Further, when the physical address corresponding to the page address is obtained from the address conversion unit 2, whether or not the physical address is existed in the buffer mrmory unit is checked. If not present, the lower rank address of the page address is changed and accessing is made again to the buffer memory unit to check whether or not the same physical address as that obtained from the unit 2, and if present, the buffer memroy block corresponding to the physical address is made ineffective.
COPYRIGHT: (C)1981,JPO&Japio
JP54091418A 1979-07-18 1979-07-18 Buffer memory control method Expired JPS5922315B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54091418A JPS5922315B2 (en) 1979-07-18 1979-07-18 Buffer memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54091418A JPS5922315B2 (en) 1979-07-18 1979-07-18 Buffer memory control method

Publications (2)

Publication Number Publication Date
JPS5616982A true JPS5616982A (en) 1981-02-18
JPS5922315B2 JPS5922315B2 (en) 1984-05-25

Family

ID=14025817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54091418A Expired JPS5922315B2 (en) 1979-07-18 1979-07-18 Buffer memory control method

Country Status (1)

Country Link
JP (1) JPS5922315B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58150186A (en) * 1982-03-03 1983-09-06 Nec Corp System for controlling buffer memory
JPS6451544A (en) * 1987-08-22 1989-02-27 Nec Corp Hierarchical cache device
JPS6451543A (en) * 1987-08-22 1989-02-27 Nec Corp Hierarchical cache device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510973A (en) * 1991-08-15 1996-04-23 Fujitsu Limited Buffer storage control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58150186A (en) * 1982-03-03 1983-09-06 Nec Corp System for controlling buffer memory
JPS6213699B2 (en) * 1982-03-03 1987-03-28 Nippon Electric Co
JPS6451544A (en) * 1987-08-22 1989-02-27 Nec Corp Hierarchical cache device
JPS6451543A (en) * 1987-08-22 1989-02-27 Nec Corp Hierarchical cache device

Also Published As

Publication number Publication date
JPS5922315B2 (en) 1984-05-25

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