JPS55105761A - Address conversion system - Google Patents

Address conversion system

Info

Publication number
JPS55105761A
JPS55105761A JP1375179A JP1375179A JPS55105761A JP S55105761 A JPS55105761 A JP S55105761A JP 1375179 A JP1375179 A JP 1375179A JP 1375179 A JP1375179 A JP 1375179A JP S55105761 A JPS55105761 A JP S55105761A
Authority
JP
Japan
Prior art keywords
register
address
bit
memory
converted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1375179A
Other languages
Japanese (ja)
Inventor
Yutaka Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1375179A priority Critical patent/JPS55105761A/en
Publication of JPS55105761A publication Critical patent/JPS55105761A/en
Pending legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To increase the degree of freedom of program and to enclose large logic address space in the mounted memory capacity, by providing the bit designating whether the logic address is converted into physical address or not, with the register storing the status of the program under execution.
CONSTITUTION: The bit designating whether the logic address is converted into physical address or not is provided at the register 20 storing the status of the program under execution. When this bit is not in relocation mode, and it is in relocation mode but if the specific bits of the memory address register are all "0", the contents of the memory address register 9 are transferred to the memory unit 11 as it is. Further, in reverse case, a given register is selected among the relocation register group 15, the selected content and the data represented in the remaining bit of the memory address register 9 are added and converted into physical address, which is transferred to the main memory unit 1.
COPYRIGHT: (C)1980,JPO&Japio
JP1375179A 1979-02-08 1979-02-08 Address conversion system Pending JPS55105761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1375179A JPS55105761A (en) 1979-02-08 1979-02-08 Address conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1375179A JPS55105761A (en) 1979-02-08 1979-02-08 Address conversion system

Publications (1)

Publication Number Publication Date
JPS55105761A true JPS55105761A (en) 1980-08-13

Family

ID=11841946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1375179A Pending JPS55105761A (en) 1979-02-08 1979-02-08 Address conversion system

Country Status (1)

Country Link
JP (1) JPS55105761A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5817585A (en) * 1981-07-21 1983-02-01 Hitachi Ltd Virtual storage processor
JPS60146333A (en) * 1984-01-09 1985-08-02 Fujitsu Ltd Designating method of memory area
JPS6158043A (en) * 1984-07-28 1986-03-25 Fujitsu Ltd Register address converter circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5817585A (en) * 1981-07-21 1983-02-01 Hitachi Ltd Virtual storage processor
JPH0150936B2 (en) * 1981-07-21 1989-11-01 Hitachi Ltd
JPS60146333A (en) * 1984-01-09 1985-08-02 Fujitsu Ltd Designating method of memory area
JPS6158043A (en) * 1984-07-28 1986-03-25 Fujitsu Ltd Register address converter circuit

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