JPS5671141A - Instruction word read control system - Google Patents

Instruction word read control system

Info

Publication number
JPS5671141A
JPS5671141A JP14752979A JP14752979A JPS5671141A JP S5671141 A JPS5671141 A JP S5671141A JP 14752979 A JP14752979 A JP 14752979A JP 14752979 A JP14752979 A JP 14752979A JP S5671141 A JPS5671141 A JP S5671141A
Authority
JP
Japan
Prior art keywords
instruction
read
address
main memory
instruction word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14752979A
Other languages
Japanese (ja)
Inventor
Tomoyoshi Inasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14752979A priority Critical patent/JPS5671141A/en
Publication of JPS5671141A publication Critical patent/JPS5671141A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To read a corresponding instruction word by one instruction read independently of the instruction address, by giving the address, which is obtained by adding 1 to the original address, as the instruction address for the main memory.
CONSTITUTION: A corresponding one-byte instruction word is read into the instruction register by one read in respect to one-byte instruction words. However, in respect to two-byte instruction words, though corresponding two bytes can be read by one instruction read if the least significant bit of the instruction address is "0", they are read from the main memory by two instruction reads conventionally if the said least significant bit is "1". One-stage register 12 is provided for the lower byte of main memory 1, and the address obtained by adding 1 to the original address is given as the instruction address for main memory 1 by incrementer 14. As the result, the corresponding instruction word is read from main memory 1 by one instruction read independently of the instruction address.
COPYRIGHT: (C)1981,JPO&Japio
JP14752979A 1979-11-14 1979-11-14 Instruction word read control system Pending JPS5671141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14752979A JPS5671141A (en) 1979-11-14 1979-11-14 Instruction word read control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14752979A JPS5671141A (en) 1979-11-14 1979-11-14 Instruction word read control system

Publications (1)

Publication Number Publication Date
JPS5671141A true JPS5671141A (en) 1981-06-13

Family

ID=15432366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14752979A Pending JPS5671141A (en) 1979-11-14 1979-11-14 Instruction word read control system

Country Status (1)

Country Link
JP (1) JPS5671141A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61282932A (en) * 1985-06-07 1986-12-13 Fujitsu Ltd Address counter control system
JPS6383875A (en) * 1986-09-29 1988-04-14 Toshiba Corp Picture processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61282932A (en) * 1985-06-07 1986-12-13 Fujitsu Ltd Address counter control system
JPS6383875A (en) * 1986-09-29 1988-04-14 Toshiba Corp Picture processor
JPH0524538B2 (en) * 1986-09-29 1993-04-08 Tokyo Shibaura Electric Co

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