JPH0524538B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image processing apparatus that performs image processing of an image, and particularly relates to an image processing apparatus that performs bitmap image processing.

(Prior Art) Image processing devices that display or process image data bit by bit are becoming popular.
Conventionally, such image processing has often been performed on a bit-by-bit basis, but in recent years, with the aim of increasing speed, processing has been increasingly performed on a word-by-word basis.

In order to perform such image processing in units of words, a so-called bit boundary access function is required to extract image data in units of words from arbitrary bit positions.

Conventionally, a circuit as shown in FIG. 6 has been used to realize this bit boundary access. This circuit accepts multiple bits of input data 10
A register 101 that latches 0, output data 102 of this register 101, and input data 100
and a barrel shifter 103 that receives as input.

The operation of this circuit will be briefly explained. It is now assumed that image data is stored in a memory (not shown) in a state as shown in FIG. Here, A, B, C
are word unit data in memory, D is data that exists across A and B and should be extracted by bit boundary access, and E is data that exists across B and C. exists,
This is data to be extracted by bit boundary access.

FIG. 8 is a timing chart showing the operation timing of the circuit shown in FIG. Barrel shifter 103
Since memory contents A and B are input in parallel at the second timing of the clock signal 111,
D can be extracted. Furthermore, at the third timing of the clock signal 111, the memory contents B and C are input in parallel to the barrel shifter 103, so that E can be extracted.

In this manner, the conventional circuit shown in FIG. 6 can perform bit boundary access while sequentially accessing the memory.

By the way, in systems that handle images with multiple colors or shading, multiple bits are generally assigned to one pixel to form multiple color planes. In this case, as many circuits as there are planes are required to perform bit boundary access as shown in Figure 6, and these multiple circuits operate in parallel when performing bit boundary access. .

With the recent development of integrated circuit technology, integrated circuits that can perform bit boundary processing in parallel for image memory systems having multiple planes are now appearing, and this is expected to greatly contribute to reducing system costs.

However, due to the conventional bit boundary processing implementation, the circuit lacks flexibility and severely limits the configuration of the memory system. For example, one word
A system that uses 16 bits and processes four planes simultaneously can be configured with other memory configurations, such as 8
Bit x 8 sides, 32 bit x 2 sides, 64 bit x 1
It is impossible to try to achieve this using surfaces, etc. This is because the configuration of barrel shifter 103 is fixed depending on the number of bits in one word of the memory system.

(Problems to be Solved by the Invention) As described above, the conventional method has a drawback in that it is not possible to perform bit boundary processing using various memory systems with different word lengths.

The present invention has been made in consideration of the above circumstances, and its purpose is to provide an image processing device that can perform bit boundary processing on various memory systems with different word lengths. It's about doing.

[Structure of the Invention] (Means for Solving the Problems) An image processing device of the present invention includes a first image data bus line to which image data is transferred, and a first image data bus line to which image data is transferred;
a register connected to the image data bus line for recording the image data; first and second selectors connected to the output line of the register and the first image data bus line, respectively; and a register for recording the image data; a third selector to which the second image data bus line and the first image data bus line are connected; and a third selector to which the output lines of the second and third selectors are connected. At least one image processing section is provided, which includes data shifting means for shifting the output data of the selector No. 3 by an arbitrary number of bits and outputting the shifted data.

(Function) In the image processing device of the present invention, the output data of the second selector is output data from the register,
Further, by using the output data of the third selector as the input data to the register, bit boundary processing can be performed on the word length of the bus width of the input data.

On the other hand, by selecting external input data as the output of the third selector, bit boundary processing can be performed in units of arbitrary multiples of the bus width of the input data to the register.

(Example) The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one image processing section used in an image processing apparatus according to the present invention. In the figure, 11 is a first bus line to which 1 word, n bits of image data is transferred. The image data transferred to this bus line 11 is supplied in parallel to an n-bit configured register 12, one input terminal of each of the first selector 13 and third selector 14, and the other input terminal of the second selector 15. .

The output data of the register 12 is transmitted to the other input terminal of the first selector 13 and the second selector 15.
is supplied in parallel to one input terminal of the Further, image data to be transferred to the second bus line 16 is supplied to the other input terminal of the third selector 14 .

The first, second and third selectors 13, 15,
14 selectively outputs data at one or the other input terminal based on a control signal. and,
The selection output data of the first selector 13 is output to the outside, and the selection output data of the second and third selectors 15 and 14 are supplied to the barrel shifter 17 in parallel. This barrel shifter 17 shifts the 2n-bit data from the second and third selectors 15 and 14 by arbitrary bits, extracts it as n-bit data, and outputs it.

In the image processing configured in this way, the second selector 15 is controlled by a control signal to select the output data of the register 12, and the third selector 14 is controlled to select the data of the first bus line 11. By controlling the selection using a control signal, this circuit becomes equivalent to the conventional circuit shown in FIG. 6. That is, bit boundary processing corresponding to the number of bits of image data transferred from the memory to the bus line 11 can be performed.

On the other hand, the third selector 14 selects the second bus line 1
When the control signal is used to select the image data to be transferred to step 6, the number of bits of input image data n
Bit boundary processing can be performed in arbitrary multiples of , ie, 2n, 3n, 4n, . . . . This will be explained below.

Figure 2 shows that the two image processing units shown in Figure 1 above can be used to perform bit boundary processing for both 1 word, 8 bits x 2 screens and 1 word, 16 bits x 1 screen memory system. I did it like this,
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, reference numerals 20 and 30 are image processing units each consisting of first and second bus lines, registers, first, second, and third selectors, and a barrel shifter, similar to those shown in FIG. 1 above. In one image processing section 20, the alpha alphabet A is added to the end of the reference numerals in the parts corresponding to those in FIG. 1, and in the other image processing section 30, the alpha alphabet B is added to the end of the reference numerals. In this case, the number of bits n of the image data transferred on the first and second bus lines 11 and 16 is 8, and
Each of bits 3, 15, and 14 has an 8-bit structure, and the barrel shifter 17 has a 16-bit structure, which is twice that.

Here, the output data of the first selector 13A in one image processing section 20 is
The output data of the first selector 13B in the other image processing section 30 is supplied to the other input end of the third selector 14B via the second bus line 16B in the other image processing section 30. 20 through the second bus line 16A to the third selector 14A.
is supplied to the other input terminal of

Next, the operation of the apparatus configured as described above will be explained.

First, in one and the other image processing sections 20 and 30, the second selectors 15A and 15B are controlled by a control signal to select the output data of the registers 12A and 12B, respectively, and the third selectors 14A and 14B is the first bus line 11A,1
Control signals are used to select each of the 1B data. At this time, each of the one image processing section 20 and the other image processing section 30 has a configuration equivalent to the conventional circuit shown in FIG. 6. That is, in this case, the number of bits of image data from the memory transferred on each bus line 11A, 11B,
That is, bit boundary processing corresponding to 8 bits can be performed in parallel. Here, FIG. 3a shows the arrangement of data on the memory that is subjected to bit boundary processing in one image processing section 20, and FIG. This shows the arrangement of data in memory. That is, in Fig. 3a and b, Ax, Ay, Az, ... are each one word data of one plane with 8-bit configuration, and Bx,
By, Bz, . . . are 1 word data of the other plane, which also has an 8-bit configuration.

Next, as shown in FIG. 4a, each word consists of 8-bit data Ap and Bp, Aq and Bq,
The operation when performing bit boundary processing on a memory system of 1 word, 16 bits x 1 plane, consisting of . . . , will be explained.

First, in the first cycle, word data Ap and Bp on the memory shown in FIG. are output to the first bus line 11B in the other image processing section 30, respectively.

In the second cycle, these data are transferred to register 1.
2A and 12B, and Fig. 4a
The next word data Aq, Bq on the memory shown in
are read out in parallel, bus lines 11A and 11B
are output respectively. At this time, in one image processing section 20, the first selector 13A transfers the data on the first bus line 11A to the second selector 1.
5A selects the output data of the register 12A, and the third selector 14A selects the data of the second bus line 16A using respective control signals. Furthermore, in the other image processing unit 30, the first selector 13B receives the output data of the register 12B, the second selector 15B receives the output data of the register 12B, and the third selector 14B receives the data of the second bus line 16B. are controlled by each control signal to select each. As a result, in the image processing unit 20, the barrel shifter 17A is supplied with 8-bit data Ap and Bp, so that the barrel shifter 17A receives 8-bit data spanning both data Ap and Bp, as shown in FIG. 4b. Data of Cp
can be extracted.

At the same time, the image processing section 30 supplies 8-bit data Aq and Bq to the barrel shifter 17B, so that the barrel shifter 17B outputs 8-bit data spanning both data Aq and Bp as shown in FIG. 4b. Bit data Cq can be extracted.

In this way, bit boundary processing for 16-bit data can be executed within the second cycle period. Thereafter, by repeating the same operation, each bit boundary process for one word of 16 bits of data is successively performed.

If the amount to be shifted exceeds 8 bits,
By further performing a word-by-word shift after the bit boundary shift described above, it becomes possible to process an arbitrary bit shift amount.

In addition, in the above embodiment, this invention is expressed as 1 word, 8
We have described a memory system that can perform bit boundary processing for both 2-bit screen, 1 word, and 16-bit screen. As a result, bit boundary processing can be performed for any memory system having a 1-word n-bit configuration or a 1-word (n×m) bit configuration.

Further, by appropriately inserting selectors between the image processing units, bit boundary processing can be performed for three types of memory systems having different word lengths.

FIG. 5 is a block diagram showing the configuration of an applied example of the present invention. In this application example device, four image processing units 40, 50,
60 and 70 are provided, these are connected in cascade, and between the image processing units 60 and 50, output data of the first selector 13 (not shown in FIG. 5) in the image processing unit 60 and image processing are provided. A selector 80 that performs selection with the output data of the first selector 13 (also not shown) in the image processing section 40 is provided between the image processing sections 70 and 40.
(not shown) and the output data of a first selector (not shown) in the image processing section 40 are respectively provided.

In such a configuration, by selecting the output data of the first selector 13 in the image processing section 60 with the selector 80 and selecting the output data of the first selector 13 in the image processing section 40 with the selector 90, This device performs bit boundary processing for a memory system of 32 bits per word x 1 plane. On the other hand, the selector 80 selects the output data of the first selector 13 in the image processing section 40, and the selector 90 selects the output data of the first selector 1 in the image processing section 60.
By selecting output data No. 3, this device performs bit boundary processing for a memory system of 16 bits per word x 2 planes. moreover,
By using each image processing section independently in the same manner as above, this device can process 8 bits per word x
Performs bit boundary processing for the four-sided memory system. Therefore, this applied example device performs bit boundary processing for three types of memory systems having different word lengths.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide an image processing device that can perform bit boundary processing on various memory systems in which the word length of one word is different.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one image processing section used in an image processing apparatus according to the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 4 is a diagram for explaining the operation of the above embodiment device, FIG. 5 is a block diagram showing the configuration of an applied example of this invention, FIG. 6 is a block diagram of a conventional device, and FIG. 7 is a diagram of the above conventional device. FIG. 8 is a timing chart of the conventional device described above. 11...First bus line, 12...Register, 13...First selector, 14...Third selector, 15...Second selector, 16...Second
bus line, 17...barrel shifter, 20,3
0... Image processing section.

Claims (1)

[Scope of Claims] 1. A first image data bus line to which one word n bits of image data is transferred; and a first image data bus line connected to the first image data bus line;
a register for storing the image data; first and second selectors to which the output line of the register and the first image data bus line are respectively connected; a second image data bus line; Image data bus line and the first
The third selector to which the image data bus line of the above is connected is connected to the output lines of the second and third selectors, and the output lines from the second and third selectors are connected to the third selector.
and data shifting means for shifting 2n-bit data by an arbitrary number of bits and extracting and outputting it as n-bit data, the bits corresponding to the n-bit width of the image data transferred to the first image data bus line. - When performing boundary processing, select the output data of the register with the second selector, and
The data on the first image data bus line is selected by the third selector, and bit boundary processing is performed in units of arbitrary multiples of the n-bit width of the image data transferred to the first image data bus line. If carried out, the above 1st
The selector selects the data on the first image data bus line or the output data of the register and outputs it to the outside, and the second selector selects the output data of the register, and the third An image processing apparatus characterized in that a selector is configured to select data on the second image data bus line. 2 It has a first image processing section and a second image processing section, each of which is connected to a first image data bus line to which image data of 1 word and n bits is transferred, and connected,
a register for storing the image data; first and second selectors to which the output line of the register and the first image data bus line are respectively connected; a second image data bus line; Image data bus line and the first
The third selector to which the image data bus line of the above is connected is connected to the output lines of the second and third selectors, and the output lines from the second and third selectors are connected to the third selector.
and a data shift means for shifting 2n-bit data by an arbitrary number of bits and extracting and outputting it as n-bit data. The first image data bus line of the second image processing section is connected to the second image data bus line.
Connect the output line of the selector to the second image data bus line of the first image processing section, and perform bit boundary processing corresponding to the n-bit width of the image data transferred to each of the first image data bus lines. In this case, each second selector selects the output data of each register, and each third selector selects the data of each first image data bus line, and each of the above-mentioned first image data When performing bit boundary processing in units of arbitrary multiples of the n-bit width of the image data transferred to the bus line, in the first image processing section, the first selector selects the first image data bus line. select the data, select the output data of the register with the second selector, select the data of the second image data bus line with the third selector, and in the second image processing section, select the output data of the register with the first selector. select the output data, cause the second selector to select the output data of the register, and select the output data of the register with the second selector;
An image processing device characterized in that the selector is configured to select data on a second image data bus line.