JPH0221633B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to an image enlarging/reducing device for enlarging or reducing image information at high speed. Configuration of conventional examples and their problems In recent years, there has been an increase in the number of devices that edit and process data such as handwritten characters and graphics by treating it as image information without encoding it. In this field, there is an increasing demand for processing such as high-speed scaling of image information. First, a conventional image scaling method will be explained. In the following description, it is assumed that pixels exist only on grid points, and the coordinates of the grid points are represented by integers. As shown in Figure 1, an image X consisting of n pixels x ₁ , x ₂ , ... x _o arranged one-dimensionally on a grid point
Let us consider the case of converting into an image Z consisting of m Z ₁ , Z ₂ , . . . Z _n . In the example shown, m=8, m=5
This is the case of reduction. The following methods can be considered to perform such conversion. That is, as shown in FIG. 2, a mapping pattern (also called a mask pattern) P is prepared in which 1 is placed at the position of pixels to be extracted from the original image X and 0 is placed at the position of pixels not to be extracted. This is a method of extracting necessary pixels 22 from the image and compressing them to obtain an output image Z. To get the mapping pattern from X _i
For example, according to the formula j=[5/8(i-1/2)]+1...(1), when i is changed from 1 to 8 as shown in the table, j is converted to Z _j . Calculate it and set it to 1 when j changes and 0 when it does not. However, [α] in formula (1) represents the maximum integer that does not exceed α. In general, calculation can be performed according to the formula j=[m/n(i-1/2)]+1...(2).

[Table] In the case of enlargement, as shown in Figure 3, if the mapping pattern is 1, the pixel X _i of the original image is updated; if it is 0, the pixel X i of the original image is updated.
All you have to do is repeat X _i . Actual scaling using the mapping pattern P can be performed by the circuit shown in FIG. The mapping pattern is calculated in advance by an external processor and stored in the shift register 42 via the data bus 41. This data is shifted to the left by clock _c3 , and the data at the left end is returned to the right end and circulated. The original image data is stored in the shift register 43 via the bus 49 and shifted to the left by the clock e. Output data is created in a shift register 44 that is shifted to the left by clock g, and read out via bus 48. The control signal h is 0 for enlargement and 1 for reduction. To explain the case of reduction, the clocks are c ₁ , c ₂ ,
C is applied in the order of ₃ , and this is considered as one cycle. Since h is 1, clock c ₁ passes through OR gate 471 and appears on clock e, transfers the first data x ₁ of shift register 43 to buffer 50, and simultaneously shifts shift register 43 to the left and transfers the leftmost data of 43.
Let's say x ₂ . Initially, since clock b is 1, clock _c2 passes through OR gates 45 and 461 and appears on clock g, and buffer 50 is sent to shift register 44.
Take in the value x ₁ . The clock _c3 circulates to the left through the shift register 42 and sets the leftmost data to 0. In the next cycle, first the clock _c1 causes a buffer of 5.
0 becomes x ₂ , and the left end of the shift register 43 becomes x ₃ . Since clock b is 0, clock _c2 does not appear on clock g and shift register 44 does not change. The shift register 42 is rotated to the left by the clock _c3 , and the left end becomes 1. Similarly, after 8 cycles, the output data is stored in the shift register 44.
Since x ₁ , x ₃ , x ₄ , x ₆ , and x ₇ are generated, these are output through the bus 48 to clear the contents. Batsuhua 50 has x ₈ remaining. Since the shift register 43 becomes empty, new data is input through the bus 49.
Since the shift register 42 has returned to its original state, it performs the same processing as above to generate the next output data. In the case of expansion, the clocks are applied in the order of c ₂ , c ₁ , and c ₃ and this is considered as one cycle. Since the control signal h is 0, the OR gates 46 ₂ and 47 ₂ are opened, the clock c ₁ appears on g, and the mapping pattern 1 appears on e.
Clock C ₂ appears only when . Data from the buffer 50 is loaded into the shift register 44 every clock _c1 . Therefore, after 8 cycles, the output data x ₁ , x ₁ , x ₂ , x ₃ ,
Since x ₃ , x ₄ , x ₅ , and x ₅ are generated, they are output through the bus 48. In the buffer 50, x ₅ remains, and in the shift register 49, x ₆ , x ₇ , and x ₈ remain. However, the above-mentioned enlargement/reduction method has the disadvantage of being slow because it processes one pixel at a time. OBJECT OF THE INVENTION An object of the present invention is to execute image enlargement/reduction processing at high speed. Structure of the Invention The present invention includes a storage device that stores image information, a first register that stores a mapping pattern that indicates the position of information to be extracted when reducing the image, and indicates the number of times that the information should be copied when enlarging the image. The above object is achieved by providing a second register that stores the final pixel data of the pixel data string generated by the scaling process. DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram of an image enlarging/reducing apparatus according to an embodiment of the present invention. The main components are:
An input register 52, a control register 54, an enlargement/reduction circuit 55 which will be explained using FIGS. 18 to 22,
They are an auxiliary register 58 and an arithmetic circuit 59. Original image data is stored in input register 52 via bus 51. The mapping pattern is stored in control register 54 via bus 53. Input register 5
The original image data in 2 is enlarged or reduced together with the data in the auxiliary register 58 by the enlargement/reduction circuit 55 controlled by the mapping pattern in the control register 54, stored in the output register 56, and transmitted via the bus 57. Read out. The auxiliary register 58 extracts and stores the final pixel data of the data 51a generated by the enlargement/reduction circuit 55. The arithmetic circuit 59 receives the output data 52 of the control register 54.
The final pixel data is extracted using a and set in the register 58. Next, each part will be explained in more detail. The basic concept of the enlargement/reduction circuit 55 is shown in FIGS. 6 to 17. 6 to 11 are examples of enlargement circuits, and FIGS. 12 to 17 are examples of reduction circuits. First, the information expansion method will be explained. First, the original image X is divided into x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ ,
x ₇ , and the reference mask pattern P is 1, 0, 1,
Consider the case of 0, 0, 0, 1, 0. As shown in FIG. 6, each element of the matrix is designated by M _ij with a subscript i in the vertical direction and j in the horizontal direction. The original image X initially exists in the row i=0, moves within the matrix from the i-th row to the i+1-th row, and becomes an enlarged image Y=x ₀ , x ₀ , x ₁ , x ₁ , x ₁ , x ₁ , x ₂ ,
x ₂ . When moving from the i-th row to the i+1-th row, if the reference mask pattern P _i =1, all elements of the i-th row are moved to the i+1-th row. If P _i =0, then j=0
The elements from j to i-1 are directly moved to the i+1th line, and the elements from j=1-1 to the right end are shifted by one element to the right and moved to the i+1th line. This operation is performed up to the row i=7, and an enlarged image Y is obtained as an output from the matrix. If we apply the actual values according to the above principle and look at how they are expanded, we get the following. (1) In the row where i=0, P ₀ =1, so all elements in the 0th row are moved to the 1st row. Therefore, the rows where i=1 are x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ , and x ₇ . (2) In the row where i=1, P ₁ = 0, so to M ₂₀ ,
M ₁₀ is transferred as is, and M ₁₀ is transferred to M ₂₁ ~ M ₂₇ .
~M ₁₇ are transferred in order. Therefore, the row of i=2 is x ₀ , x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ . (3) Since P ₂ =1 in the row where i=2, all elements in the second row are moved to the third row. Therefore, the row of i=3 is x ₀ , x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ . (4) By similarly processing the rows i=3 to 7, the output from the matrix is Y=x ₀ ,
x ₀ , x ₁ , x ₁ , x ₁ , x ₁ , x ₂ , x ₂ can be obtained. Next, an information enlarging circuit, which is a main part in an embodiment of the present invention, will be explained. FIG. 7 shows the wiring of an enlarged circuit which is a main part in an embodiment of the present invention. In FIG. 7, ₁₀₀ to ₁₀₇ are information input terminals to which image information _x0 to _x7 to be enlarged are applied, and ₁₁₀ to
11 ₇ is 2 according to the reference mask pattern P ₀ to P ₇
a control signal input terminal, 12, to which a value control signal is applied;
₀ to ₁₂₇ are inverters. 13 is provided at the position of element M _j,k (however, j and k are both integers, 1≦j≦7, j>k) of a matrix with 8 rows and 8 columns, and it also transmits information sent from above. It is a means for transmitting information downward, and may simply be a signal line. 14 is the matrix element M _s,t (however,
s and t are both integers and are provided at positions where 0≦s≦7, s≦t), and a control signal corresponding to the reference mask pattern P _s sent through the control signal input terminal 11 _s . information selection means for selecting either the information located in the matrix element M _s-1,t-1 or the information located in the matrix element M _s-1,t according to a s _and b _s ; It is composed of logic elements 14a, 14b, 14c, and 14d as shown in the figure. 15 ₀ to 15 ₇ are output terminals from which the enlarged image Y is obtained. The information selection means 14 will be described below with reference to FIG.
The configuration will be explained in more detail. As shown in FIG. 9, when the control signal a s sent through the control signal input terminal 11 _s is "0" and the control signal _{b s is} "1", the information selection means 14 selects (a _s , b _s ) = (0, 1), the matrix
When the information c located at M _s-1,t-1 is input, and the control signal a _s is "1" and the control signal b _s is "0", that is, (a _s , b _s ) = (1, 0 ), the matrix
Selectively input information d located at M _s-1,t . The operation of the above configuration will be explained below. Note that the reference mask pattern P is 1, 0, 1, 0,
0, 0, 1, 0, and finally the enlarged information x ₀ , x ₀ ,
Suppose we obtain x ₁ , x ₁ , x ₁ , x ₁ , x ₂ , x ₂ . First, as shown in FIG. 10a, the information input terminal 1
The original image information x ₀ to x ₇ is sent to the information selection means 14 ₀ to 14 ₇ via signals ₀ 0 to 10 ₇ . At this time, the information selection means 14 ₀ to 14 ₇ receive (a ₀ , b ₀ )=(1, 0) as a control signal via the control signal input terminal 11 ₀ , so that the information selection means 14 ₀ ~1
₄₇ selects the information on the lines D ₀ to _{D 7} as input signals, so the original image information x ₀ to x ₇ is input, respectively. Next, as shown in FIG. 10b, the information selection means 1
The original image information x ₀ of 4 ₀ is sent to the information transmission means 13 ₀ . On the other hand _, the information selection means 14 ₈ to 14 ₁₄ receive (a ₁ ,
Since b ₁ )=(0, 1) is applied, the information on the lines c ₀ to _{c 6} is selected, so the original image information x ₀ to x ₆ is input. Next, as shown in FIG. 10c, the information transmission means 1
3 ₀ and the original image information x ₀ of the information selection means 14 ₈ are sent to the information transmission means 13 ₁ and 13 ₂ . On the other hand, the information selection means 14 ₁₅ to 14 ₂₀ receive (s ₂ , b ₂ )=(1, 0) via the control signal input terminal 11 ₂ as a control signal.
are applied, the lines D ₈ ~
Since the information on the _D14 side is selected, input the original image information x ₀ to x ₆ . Next, as shown in FIG. 10d, the information transmission means 1
Original image information of 3 ₁ to 13 ₂ and information selection means 14 ₁₅
x ₀ and x ₁ are sent to information transmission means 13 ₃ to 13 ₅ . On the other hand, the information selection means 14 ₂₁ to 14 ₂₅ receive control signals as control signal input terminals 11 ₃ (a ₃ , b ₃ ).
By applying =(0, 1), the information on the lines c ₇ to _{c 11} is selected, so the original image information x ₁ to x ₅ is input, respectively. Next, as shown in FIG. 10e, the information transmission means 1
3 ₃ to 13 ₅ and original images of information transmission means 14 ₂₁
x ₀ and x ₁ are sent to information transmission means 13 ₆ to 13 ₉ . On the other hand, the information selection means 14 ₂₆ to 14 ₂₉ receive control signals as control signal input terminals 11 ₄ (a ₄ , b ₄ ).
By applying =(0, 1), the information on the lines c ₁₂ to _{c 15} is selected, so the original image information x ₁ to x ₄ is input, respectively. Next, as shown in FIG. 10f, the information transmission means 1
3 ₆ to 13 ₉ and the original image information x ₀ and x ₁ of the information transmission means 14 ₂₆ are sent to the information transmission means 13 ₁₀ to 13 ₁₄ , respectively. On the other hand, information selection means 14 ₃₀ ~1
4 ₃₂ selects the information on the lines c ₁₆ to c ₁₈ by applying (a ₅ , b ₅ ) = (0, 1) as a control signal through the control signal input terminal 11, so the original Input image information x ₁ to _{x 3} respectively. Next, as shown in FIG. 10g, the information transmission means 1
The original image information x ₀ and x ₁ of 3 ₁₀ to 13 ₁₄ and the information transmission means 14 ₃₀ are sent to the information transmission means 13 ₁₅ to 13 ₂₀ . On the other hand, the information selection means 14 ₃₃ , 14 ₃₄ receive ( _{a 6 ,}
Since b ₆ )=(1, 0) is applied, the information on the lines D ₁₅ and D ₁₆ is selected, so the original image information x ₂ and x ₃ are input, respectively. Finally, as shown in FIG. 10h, the signal transmission means ₁₃₁₅ to ₁₃₂₀ and the information selection means 14
₃₃ image information x ₀ to x ₂ is transmitted to the signal transmission means 13 ₂₁ to 1
3 _{and 27} respectively. On the other hand, information selection means 1
4 selects the information on the line D ₁₉ side by applying (a ₇ , b ₇ ) = (0, 1) as a control signal via the control signal input terminal 11 ₇ , so the original image information x Enter ₂ . and output terminals 15 ₀ to 15 ₇
The original image information x ₀ , x ₀ , x ₁ , x ₁ , x ₁ , x ₁ ,
By extracting x ₂ and x ₂ as the final output, enlarged information Y can be obtained. By adopting the circuit configuration in which the information transmission means 13 and the information selection means 14 are arranged in a matrix as described above, a clock is not required even when high-speed enlargement is required, and the circuit configuration can be performed regularly. Therefore, it is suitable for LSI implementation. Also, by simply changing the control signal applied to the control signal input terminal 11,
Other enlarged information Y can be easily obtained. In the above description, the information transmission means 13 is provided for convenience of explanation, but as mentioned above, the information transmission means 1
Since 3 may be a simple wiring, the circuit shown in FIG. 7 may be replaced with the circuit shown in FIG. 11. Further, in the above description, only image information was explained, but other information may be applied to the present invention. Next, a method of reducing information will be explained. First, the original image X is divided into x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ ,
x ₇ , and the reference mask pattern P is 1, 0, 1,
Consider the case of 0, 0, 0, 1, 0. As shown in Figure 12, the vertical direction is i and the horizontal direction is j.
Each element of the matrix is designated by M _i,j with the subscript . The original image X initially exists in the row i=7, and is moved within the matrix in the direction from the i-th row to the i-1th row to obtain reduced images Y=x ₀ , x ₂ , x ₆ .
When moving from the i-th row to the i-1th row, the element at i=j is discarded if the reference mask pattern P _i is 0, and all elements to the right of i=j are shifted to the left by one element. be done. On the other hand, if the reference mask pattern P _i is 1, all elements of the i-th row at that time are moved to the i-1 row. This operation is performed for each element in the row with i=0 to obtain a reduced image Y as an output from the matrix. If we apply the actual values according to the above principle and look at the reduction, we get the following. (1) In the row where i=7, P ₇ =0, so x ₇ is discarded. In this example, there is no element M _7,8 to the right of M _7,7 , so M _6,7 is empty. Therefore i=
The row 6 is x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ . (2) Since P ₆ = 1 in the row with i=6, all elements of this row are moved to the row with i=5, so the row with i=5 has x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ . (3) In the row where i=5, P ₅ =0, so x ₅ is discarded, and all elements to the right of j=5 are shifted to the left. Therefore, the row of i=4 is x ₀ , x ₁ , x ₂ , x ₃ ,
x ₄ , x ₅ , x ₆ . By similarly processing the rows from i=4 to 0, the output from the matrix becomes Y=x ₀ ,
x ₅ and x ₆ . By considering that there is an element of 0 in the column j = 8, 0 is added to the empty part of the matrix.
can be set. Next, an information reduction circuit, which is a main part in an embodiment of the present invention, will be explained. FIG. 13 shows the wiring of the reduction circuit which is the main part in one embodiment of the present invention. In FIG. 13, 110 ₀ to 110 ₇ are information input terminals to which image information x ₀ to x ₇ to be reduced are applied;
11 ₀ to 111 ₇ are control signal input terminals to which binary control signals corresponding to the reference mask patterns P ₀ to P ₇ are applied, and 112 ₀ to 112 ₇ are inverters. 11
3 is an element M _j,k of a matrix with 8 rows and 8 columns (however,
Both j and k are integers and are provided at positions where 1≦j≦7, >k), and is an information transmission means that sends information sent from above downward, and may simply be a signal line. . 114 is the matrix element M _s,t (where s and t are both integers and 0≦s≦
7. It is provided at a position where s≦t), and
Control signal corresponding to reference mask pattern _P5 sent via control signal input terminal _111s
a fourteenth information selection means for selecting either the information located in the matrix element M _s+1,t+1 or the information located in the matrix element M _s+1,t according to a _s and b _s ;
Logic elements 114a, 114b, 1 as shown in the figure
14c and 114d. however,
The information selection means located in the 7th column of the matrix M is provided only to select whether or not to truncate image information _x7 . 115 ₀ to 115 ₇ are output terminals from which reduced image information Y is obtained. Hereinafter, with reference to FIG. 15, information selection means 1
The configuration of 14 will be explained in more detail. As shown in FIG. 15, when the control signal a _s sent through the control signal input terminal 111 _s is "0" and the control signal b _s is "1", the information selection means 114 selects (a _s , b _s ) = (0, 1), the information c located at M _s+1,t+1 of the matrix is input, while the control signal a _s is “1” and the control signal b _s is “0”. In other words, when (a _s , b _s )=(1, 0), information d located at M _a+1,t of the matrix is selectively input. The operation of the above configuration will be explained below. Note that the reference mask pattern P is 1, 0, 1, 0,
0, 0, 1, 0, and finally the reduced information x ₀ , x ₂ ,
Let us obtain x ₆ . First, as shown in FIG. 16a, the information input terminal 1
Information transmission means 113 ₀ ~ via 10 ₀ ~ 110 ₇
Original image information x ₀ to 113 ₆ and information selection means 114 ₀
~x sends out ₇ . At this time, the information selection means 114 ₀ is applied with (a ₇ , b ₇ )=(0, 1) as a control signal via the control signal input terminal 111 ₇ , so that the information selection means 114 ₀ receives the input signal. Since the information on the line C side is selected as follows, the original image information _x7 is truncated. Next, as shown in FIG. 16b, the information transmission means 1
The original image information _x0 to _x5 from ₁₃₀ to ₁₁₃₅ is sent to information transmission means ₁₁₃₇ to ₁₁₃₁₂ . On the other hand, the information selection means 114 ₁ receives the control signal as a control signal via the control signal input terminal 111 ₆ (a ₆ , b ₆ )=(1, 0).
is applied, information on the line D side is selected, so original image information _x6 is input. Next, as shown in FIG. 16c, the information transmission means 1
The original image information x ₀ to _{x 4} from 13 ₇ to 113 ₁₁ is sent to information transmission means 113 ₁₃ to 113 ₁₇ . On the other hand, the information selection means 114 ₂ receives a control signal via the control signal input terminal 111 ₅ (a ₅ , b ₅ )=(0, 1).
Since information on the line C side is selected due to the fact that is applied, original image information _x6 is input. Next, as shown in FIG. 16d, the information transmission means 1
The original image information x ₀ to _{x 3} from 13 ₁₃ to 113 ₁₆ are sent to information transmission means 113 ₁₇ to 113 ₂₀ . On the other hand, the information selection means 114 ₃ outputs (a ₄ , b ₄ )=(0, 1) via the control signal input terminal 111 ₄ as a control signal.
is applied, information on the line C side is selected, so original image information _x6 is input. Next, as shown in FIG. 16e, the information transmission means 1
The original image information x ₀ to x ₂ from 13 ₁₇ to 113 ₁₉ are sent to information transmission means 113 ₂₁ to 113 ₂₂ . On the other hand, the information selection means ₁₁₄₄ outputs (a ₃ , b ₃ )=(0, 1) via the control signal input terminal 111 ₃ as a control signal.
is applied, information on the line C side is selected, so original image information _x6 is input. Next, as shown in FIG. 16f, the information transmission means 1
The original image information x ₀ and x ₁ of 13 ₂₁ and 113 ₂₂ are sent to information transmission means 113 ₂₄ and 113 ₂₅ . On the other hand, the information selection means 114 ₅ , 114 ₆ input (a ₂ , b ₂ )=(1,
0) is applied, the lines
Since the information on the D ₁ and D ₂ side is selected, the original image information x ₂ ,
Input x ₆ respectively. Next, as shown in FIG. 16g, the information transmission means 1
13 ₂₄ original image information x ₀ is information transmission means 113 ₂₆
sent to. On the other hand, information selection means 114 ₇ , 11
4 ₈ selects the information on the lines C ₁ and C ₂ , respectively, by applying (a ₁ , b ₁ ) = (0, 1) as a control signal through the control signal input terminal 111 ₁ . Input original image information x ₂ and x ₆ , respectively. _{Finally ,} as _shown in _{FIG .}
By applying b ₀ )=(1, 0), the information on the D ₁ , D ₂ , and D ₃ sides is selected, so the original image information x ₀ , x ₂ , and x ₆ is input. Then, the reduced information Y can be obtained by taking out the information selection means 114 ₉ , 114 ₁₀ , 114 ₁₁ as the final output. As described above, by adopting the circuit configuration in which the information transmitting means 113 and the information selecting means 114 are arranged in a matrix, a clock is not required even when high-speed reduction is required. Due to its circuit configuration, it is suitable for LSI implementation. Further, other reduction information Y can be easily obtained by simply changing the control signal applied to the control signal input terminal 111. In the above explanation, the information transmitting means 113 is provided for convenience of explanation, but as mentioned above, the information transmitting means 113 may be a simple wiring, so the circuit shown in FIG. 13 may be replaced with the circuit shown in FIG. 17. Further, in the above explanation, only image information has been explained, but other information may be applied to the present invention, and it can also be used for information sampling, etc. Now, in the above reduced circuit, the mapping pattern is 1
Only the data x ₀ , x ₂ , and x ₆ are extracted, and other information about the original image is lost. Therefore, in the present invention, in order to make effective use of this information, the mapping pattern is
It is conceivable to logically OR the data at 0 and the data at 0 after that. That is, x _0,1 , x _2,3,4,5 and x _6,7 are obtained as final data. Here, x _{i, j, k,} etc. are x _i , x _j , x _k
It shows the data obtained by calculating the logical sum of . To realize this process, the wiring to the element M _i,i-1 on the left side of the diagonal element of the reduced circuit shown in Fig. 13 can be changed as shown in Fig. 18 (however, A logic 1 signal is input to point A.) Currently, the data of M _i+1,i-1 is stored as is, but by doing this, if the mapping pattern is 0, the data of M _i+1,i-1 and the data of M _i+1,i
The logical OR with the data is taken. First, the auxiliary register 58 will be explained. According to the enlarging/reducing circuit 55, which is composed of an enlarging or reducing circuit, the number of data referenced in one process as shown in FIGS. 2 and 3 depends on the mapping pattern in the case of enlarging. The number is equal to the number of 1's in the middle, and is always 8 in the case of reduction. On the other hand, the number of data generated in one process is always eight in the case of expansion, and the number of data generated in one process is equal to the number of 1s in the mapping pattern in the case of reduction. In the case of enlargement, as shown in FIG.
(represented by ) to the left, and the missing part is filled in from the next original image data. In the case of enlargement, the data is switched at 1 in the mapping pattern, and the previous data is copied at 0. Therefore,
When the first data of the mapping pattern is 0 as in 191, the final data _x5 referenced in the previous process is required. Since this data is also the final pixel data FB of the data generated in the previous process, the FB is extracted by the arithmetic circuit 59 and returned to the auxiliary register 58. When the head of the mapping pattern is 1 like 192, there is no need to return the final pixel data FB. In the case of reduction, as shown in FIG. 20, the original image data in the input register 52 is always referred to in units of 8 at each processing time, including when taking a logical sum, so all of them are replaced with new original image data each time. . When performing a logical sum in reduction, the data where the mapping pattern is 1 is logically added to the data where the mapping pattern is 0. Therefore, the beginning of the mapping pattern is 20.
If it is 0 like 1, it is necessary to logically add it to the final pixel data FB of the data generated in the previous process. Therefore, this data FB is extracted by the arithmetic circuit 59 and returned to the auxiliary register 58. In this case, the number of generated data is the sum of the number NB of 1's in the mapping pattern plus 1. In the second and third processing in FIG. 20, NB is 4 and 2, respectively, and the numbers of generated data are 5 and 3, respectively. However, for example, the first data x ₇₈₁ ' generated in the second process in Figure 20 is actually the first
The last data generated in the process FB = x ₇₈ and
It is a logical sum with x ₁ ′, and x ₇₈ must be replaced with x ₇₈₁ ′. The beginning of the mapping pattern is 1 like 202
In this case, there is no need to return the FB. To summarize the above, the arithmetic circuit 59 does not need to do anything when the head of the mapping pattern is 1, and the data in the auxiliary register 58 becomes undefined.
When the head of the mapping pattern is 0 and in the case of enlargement, the eighth pixel data of the data generated in the previous process is returned to the auxiliary register 58. If the beginning of the mapping pattern is 0 and you want to take a logical OR during reduction, calculate the number NB of 1 in the mapping pattern used in the previous process, and calculate the number NB of the data generated in the previous process + the first The pixel data is returned to the auxiliary register 58, and after the current processing is completed, the final data of the data generated in the previous processing is replaced with the first data of the data generated this time. Counting the number of 1's in the mapping pattern can be carried out by shifting the mapping pattern one bit at a time and counting the number of times a carry is set. Next, a specific circuit using the auxiliary register 58 will be shown. In the case of enlargement, the input from the left to the upper left element M ₀₀ in FIG. 7 is grounded, but as shown in FIG.
Just connect the output of When taking a logical sum by reduction, as shown in FIG. 22, to the left of the element M ₀₀ at the bottom left of FIG. 18 (however, a logic 1 signal is input to point A in the figure).
Add a circuit similar to M ₀₀ and connect the output x _M of the auxiliary register 58. The leading data x ₇₈₁ ' of the data generated by the second processing in FIG. 20 is output to _yM on the left side of _y0 . Therefore, 1 bit is added to the left of the output register and stored there. When processing the generated data, this data may also be processed. Effects of the Invention As explained above, the present invention provides a register for storing the final pixel data of the pixel data string generated by the enlargement/reduction process, thereby quickly performing the process of calculating the logical sum in the enlargement/reduction process. It has good reproducibility and is highly effective.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram showing the concept of image scaling;
Fig. 2 is a conceptual diagram showing image reduction using a conventional mapping pattern, Fig. 3 is a conceptual diagram also showing enlargement, Fig. 4 is a block wiring diagram of a conventional enlargement/reduction circuit, and Fig. 5. 1 is a block wiring diagram of an image enlarging/reducing device according to an embodiment of the present invention, FIG. 6 is a diagram showing the concept of the main part of the enlarging circuit in the same device, and FIGS. 7 to 11 are specific wiring diagrams of the same circuit. 12 is a diagram showing the concept of the reduction circuit of the main part in the same device, FIGS. 13 to 17 are specific wiring diagrams of the same circuit, and FIG. Connection diagram of the circuit, No. 19
20 are conceptual diagrams showing the process of enlargement and reduction, respectively.
FIG. 2 is a circuit diagram for explaining how to use the data in the auxiliary register when performing a logical sum in reduction. 41, 48, 49... bus, 42, 43, 44
...Shift register, 45,46,47...AND circuit, 51,53,57...Bus,
52...Input register, 54...Control register,
55...Enlargement/reduction circuit, 56...Output register,
58...Auxiliary register, 59...Arithmetic circuit, 1
4,114...Selection circuit.

Claims (1)

[Claims] 1 A storage device that stores image information, a first register that stores a mapping pattern that indicates the location of information to be extracted when reducing the image, and a mapping pattern that indicates the number of times the information should be copied when enlarging the image, and a second register that stores the final pixel data of the pixel data string generated by the pixel data string; An image enlarging/reducing device comprising an enlarging/reducing circuit that simultaneously processes and enlarges/reduces images.