JP2852050B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data operation method for mask operation processing in an image processing apparatus, and more particularly to an image processing apparatus suitable for sequential processing of mask operation.

[Conventional technology]

FIG. 2 shows an embodiment of a conventional apparatus configuration. In 3 × 3 region mask processing for the pixel of interest P ₁₁ in this configuration, first, the pixel data P from the image memory 101 ₀₀ ~P _02, P ₁₀ ~
P _12, P ₂₀ ~P ₂₂ reads (all 9 pixels) to excisional to the slave connexion sequential respective registers 103 to 105 in Shifutokurotsuku. Next, these pixel data are simultaneously processed by the mask calculator 106.
Entered, and writes the output data Q ₁₁ of the arithmetic unit in the image memory 102. This Writing processing result Q ₁₁ in the image memory 101 is because it is impossible to mask operation the next pixel data P _21.

[Problems to be solved by the invention]

As described above, in the conventional configuration, when performing the mask calculation process, a memory capacity twice as large as the amount of image data to be processed is required.

Further, there is an example in which a memory for temporarily storing the processing result is provided, and the data in the temporary storage memory is written to an area where the mask operation scanning does not affect the operation processing. In the case of performing repetitive processing such as thinning processing, parallel processing of a plurality of pixels is performed to improve the processing speed. For this reason, in this example, a temporary memory having a memory amount proportional to the product of the number of pixels to be processed in parallel and the number of pixels in one column and a memory amount proportional to the product of the number of repeated processes and the number of pixels in one column are required. I have.

Therefore, an object of the present invention is to realize a mask operation efficiently with a small memory capacity.

[Means for solving the problem]

The above issues can be accessed simultaneously with the image memory,
This is achieved by providing an auxiliary memory having a function of holding one column of original data in the image memory.

[Action]

The mask calculation process is a process of determining a pixel value of interest from information on surrounding pixels of the pixel of interest, and is 3 × 3 pixels (9 pixels in total)
This is a process of scanning an area on an image memory. For this reason, a part of the original data at the current scanning position is also used at the next scanning position.

Therefore, the auxiliary memory temporarily holds the original data until the next scan is completed. In this case, the amount of data to be held does not change even if the number of pixels of the parallel processing increases, so that the parallel mask calculation processing can be efficiently realized by the small-capacity auxiliary memory.

〔Example〕

 Hereinafter, the present invention will be described with reference to examples.

FIG. 3 shows an image processing system configuration using the image processing apparatus of the present invention. In this system, first Sukiana 202
, The binary image data is stored in the image memory 203. For this image data, CPU
Image processing (mask operation, logical operation, etc.) is performed by the image processing hardware 204 under the control of 205.

FIG. 1 shows a combination configuration of a mask operation processing unit in the image processing hardware 204 and the image memory 203, and FIG. 4 shows this operation time chart.

This mask calculation processing circuit includes an image memory 301, an auxiliary memory 302, registers 303 to 305, and a mask calculator 306.

The following shows the process for the pixel data P _11.

Mask calculation processing has already been performed on the pixel data P _{00 to} P ₀₁ , and the processing results Q _{00 to} Q
₀₁ is stored. The register 303 stores original pixel data P _{22 to} P ₂₀ , the register 304 stores original pixel data P _{12 to} P ₁₀ , and the register 305 stores original pixel data P _{02 to} P ₀₀ . . It is (n-1) "cycle in Taimuchiyato operating cycle shown in Figure 4. In this cycle, inputs the nine pixel data in the mask operation unit 306, the central pixel data P ₁₁
It calculates an operation result Q ₁₁ against, and stores the pixel data P ₁₁ and the same address of the image memory 301.

N this state, n ', following the procedure of the mask processing with respect to the pixel data P ₂₁ executed by three cycles of n ". First, in the n-th cycle, 2 plus memory address in the X-axis direction, the image memory The pixel data P ₃₁ is read out from the register 303 and the register 303 and the register
Store to 309. It reads the P ₃₀ from the auxiliary memory is a one-dimensional memory given X-axis direction address simultaneously, stores the Shifutokurotsuku 307 to the register 303. At the same time, the shift clock 307 shifts the data in the register 303 to the register 304 and shifts the data in the register 304 to the register 305. Next, in the n'th cycle, the memory address is incremented by one in the Y-axis direction, and
Stores the pixel data P ₃₂ read to the register 303 from 1, the auxiliary pixel data P ₃₁ from the register 309 memory 302
To store. Pixel data P ₃₂ to P ₃₀ in Yotsute register 303 in the 2 cycle, the register 304 pixel data P ₂₂ to P ₂₀ is, in the register 305 is stored P ₁₂ to P _10, the pixel data P ₂₁ All the data necessary for the mask operation processing is stored in the register. In the n ″ cycle, the memory address is decremented by 1 in each of the X-axis and Y-axis directions, nine pixel data are input from each register to the mask calculator 306, and the calculation result Q ₂₁ is stored in the image memory 301.

By performing the above operation while updating the address, the mask operation processing for the entire image memory can be executed on one image memory.

Next, in the example shown in FIG.
The embodiment of the mask arithmetic circuit having a processing speed 64 times faster than that of the example of FIG. 1 is realized by performing pipeline processing in a 4-stage configuration with a 4-bit configuration in the X-axis direction and performing 16-bit parallel processing at the same time. Shown in the figure.

In one memory cycle, a memory read or write operation can be performed only once. In the case of the configuration shown in FIG. 3, by accessing the auxiliary memory and the image memory simultaneously, three cycles as shown in FIG. Is performed once. On the other hand, in the example of the present embodiment shown in FIG. 5, the latch has a four-stage configuration, each memory cycle is divided into two, and the latch access is performed every 1/2 cycle, thereby each 1/2 memory cycle. The mask calculation of each stage is performed once, and the mask calculation processing is performed four times in two cycles.
This result is stored in the image memory in the third cycle.
In this case, in order to obtain a result of one pixel, 9 × 9 pixels shown in FIG. 7A are required. In order to obtain 16 pixels of the final result, 24 × 9 pixels shown in FIG. 7B are required, so that the auxiliary memory has a 4-bit configuration.

Hereinafter, based on the operation time chart shown in FIG.
The processing procedure in the circuit shown in FIG. Figure 5 in the first stage register 503a, 503b, 503c pixel data P _82, P _81, P ₈₀ is stored in the (indicating _{P 72, P 71, P 70} ) P 7 * in the register 504 and 505, P ₆ * is stored. The second stage register 51
The 0,511,512, mask operation result Q '6 _*, Q' of the first stage register data respectively _{6 *,} Q _{'5 *} is, in the third stage register 513, 514 and 515, mask operation result Q of the second-stage register data respectively " ₅ *, Q ″ ₅ *, Q ″ ₄ * is applied to the mask operation of the third-stage register data in the fourth-stage registers 516,517,518, respectively, and the result Q ₄ *, Q ₄ *, Q ₃ * is stored in the register 521. mask operation result Q _'31 of the fourth-stage register data is stored.

First, in the first _{n 1} cycle, the first-stage register data _{P 8}
*, P ₇ *, P ₆ * are sent to the mask calculator and shift clock
According to 519, the operation result Q ′ ₇ * output from the mask operation unit 506 is stored in the register 510, and at the same time, the registers 503a, 503a,
P ₈ * is shifted to the register 504 from 503 b and 503 c, and P ₇ * is shifted to the register 505 from the register 504.

Next, in the first n ₂ cycles, the second stage of the stored data Q in register _{'7 *, Q' 6 *} , Q '5 * is sent to the mask operation unit Yotsute to Shifutokurotsuku 507, the mask operation 506 The output operation result Q ″ ₆ * is stored in the register 513, and at the same time, Q ′ ₇ * is stored in the register 511 from the register 510.
The register 511 shifts Q ′ ₆ * to the register 512, respectively. At the same time, the P ₉₀ to the register 503c than the auxiliary memory X address as 5 Increase 10H, the image memory 501
More stores P ₉₁ to the register 503b.

Next, in the n'th _one cycle, the data Q " ₆₁ , Q" ₅₁ , Q " ₄₁ stored in the register of the third stage is sent to the mask calculator and output from the mask calculator 506 by the shift clock 520. that calculation result and stores the Q ₅₁ in register 51b, the Q ₆₁ to register 514 from the register 513 at the same time, the register 51
4 shifts Q ″ ₅₁ to the register 515, respectively.

Next, in the n'th ₂ cycle, the fourth stage register data Q
₅₁ , Q ₄₁ , Q ₃₁ are sent to the mask calculator and the shift clock 508 stores the calculation result Q ′ ₄₁ output from the mask calculator 506 in the register 521, and at the same time, the register 516.
The Q ₅₁ to the register 517 from shift from each register 517 and Q ₄₁ to the register 518. At the same time, the Y address is incremented by 10, and P ₉₂ is stored in the register 50 from the image memory 510.
Store to 3a. P ₉ * is stored in the first n ₂ cycles and register 503a~b by the n _'2 cycles.

Finally, in the n ″ cycle, the register 521 stores the four-stage mask processing result Q ′ ₄₁ for the pixel data P ₄₁ in the P ₄₁ data storage address in the image memory 501.

By executing repeatedly the processing of the above n _a cycle until n "cycles, it is possible to perform a four-stage mask operation 16-bit parallel processing the image memory entire image memory 1 side.

〔The invention's effect〕

As described above, according to the present invention, by using the small-capacity auxiliary memory, the mask operation and the repetition parallel processing can be executed on the large-capacity image memory.
Conventionally, high-speed image processing can be realized with small hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention, FIG. 2 is a block diagram showing an embodiment of an image processing apparatus having a conventional configuration, and FIG. FIG. 4 is an operation time chart of the embodiment shown in FIG. 1, FIG. 5 is a block diagram showing an embodiment of a four-stage repetitive image processing apparatus according to the present invention, and FIG. Is the operation time chart of the embodiment of FIG. 5,
FIG. 7 is an explanatory diagram showing a pixel configuration at the time of mask calculation processing in the embodiment of FIG. 101,301,501 …… Image memory, 302,502 …… Auxiliary memory,
103 to 105,303 to 305,309,503 to 505,509,518,521 ... Register, 106,306,506 ... Mask arithmetic unit, 107,307,308,50
7,508,519,520 …… Shift clock.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Mitsuo Oyama 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (58) Field surveyed (Int. Cl. ⁶ , DB name) G06T 5/20

Claims (1)

(57) [Claims] An image memory for storing a plurality of pieces of pixel information;
With reference to surrounding pixel information of the plurality of pixel information,
A mask calculator for performing a mask calculation on the target pixel information of the plurality of pieces of pixel information, and connected to the image memory and the mask calculator, each register latching the pixel information output from the image memory; A register group for supplying data to the mask computing unit while shifting the pixel information between the registers, wherein the image processing device is connected to the image memory and can be accessed in synchronization with the access to the image memory And a part of the plurality of pieces of pixel information is stored in the auxiliary memory, and the pixel information read from the image memory in one memory cycle and the pixel information read from the auxiliary memory are stored in the auxiliary memory. An image processing apparatus for writing to one of the registers.