JPH0236423A - Saving/restoring register address generation circuit - Google Patents

Abstract

PURPOSE:To speed up a saving/restoring processing by obtaining the address of a register saved/restored next through the use of a priority encoder. CONSTITUTION:At the time of saving the register, for example, save mask data is loaded on a mask register 103, and the output of a zero detection circuit 106 is checked. Since the priority encoder 104 outputs the address of the register 103 to be saved if the content of the register 103 does not show zero, the address is selected so that it becomes the output of a multiplexer 102, and the content of a register file 101 is read and saved in a main memory. A decoder 105 simultaneously designates the bit of the mask register 103 corresponding to the selected content of the register and clears the bit by a subsequent cycle. Thus, the address of the register, which is the object of saving next, can be obtained from the output of the priority encoder 104 in the subsequent cycle. Thus, the processing can be speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device that has registers visible to a plurality of software, and particularly relates to generation of register addresses thereof.

(Prior Art) Conventionally, register address generation during this type of register save/restore has been performed using a counter that holds the register address and a save/restore mask that specifies the register to be saved/restored bit by bit. A common method is to use a shift register that holds data.

First, this method will be explained with reference to FIG.

In FIG. 2, 201 is a register file, 202 is a multiplexer, 203 is an address counter, 204 is an incrementer/decrementer, 205 is a work register, 206 is a shifter, and 207 is a test condition multiplexer. .

In FIG. 2, a register file 201 stores software-visible registers, and a register address multiplexer 202 selects one register address from among various register addresses in the instruction processing unit. The address source has an address counter register 203, and an incrementer/decrementer 2
04 allows the contents of the rear address counter register to be increased or decreased 1, work register 20SGf, *
- A register that holds the copy/restore mask data, and has the function of shifting its contents by one bit to the left or right using the register 206.

Next, consider the case where the contents of the register file are saved to the main memory using the bit contents of the save/restore mask data using the hardware configuration shown in FIG. .

First, if the contents of the work register 205 are save/restore mask data, the address counter 203
Load the initial value into. J next 1 work register 205
The least significant bit of 1 is input to the test condition multiplexer 207 via the signal line 29, and examined by the test concentrator multiplexer 207.1 Depending on the test conditions, firmware control is divided into two directions. When the above bit is 11, the contents of the register specified by the address counter 203 are read out and transferred to the main memory. When the above bit is %OI, no operation is executed. , the firmware again controls the increment of the contents of the address counter 203 and the work register 20.
1. Shift the contents of 5 to the right. Work register 20
The above described control is repeated until all bits of 5 have been examined. .

(Problems to be Solved by the Invention) The above-described conventional save/restore register address generation circuit does not process each bit of the save/restore mask data even if the number of registers to be saved/restored is one. In order to perform the checking operation, the structure is such that a firmware processing loop must be executed as many times as the number of bits included in the save/restore mask data. .

This shortcoming has the disadvantage that it is not possible to increase the speed in terms of performance, especially when the number of bits in tl in the mask data is small. .

An object of the present invention is to specify a save/return register from among the registers inside an information processing device.
Keep the restore mask data word in the mask register, examine the contents of the mask register, and scan from the right or left end of the register to find the first bit t11.
Output the position number of K and clear the bit of the mask register corresponding to the currently selected register.
Therefore, it is an object of the present invention to provide a save/restore register address generation circuit configured to eliminate the above-mentioned drawbacks and increase the speed.

(Means for Solving the Problems) A save/restore register address generation circuit according to the present invention has the following features:
It is configured to include a mask register, a priority encoder, a decoder, and a zero detection circuit. .

The mask register is used to hold a word that selects the register to be saved/restored from the register file1.The priority encoder examines the contents of the mask register and scans from the right or left end to select the first one found. The 6-bit j direct outputs the number at position 11jl. .

The decoder is for clearing the contents of the mask register according to the output of the priority encoder.

. The zero detection circuit is for detecting that the contents of the counter register are zero. .

(Example) Next, the present invention will be explained with reference to the drawings. .

FIG. 1 is a block diagram showing an embodiment of a save/restore 7 register address generation circuit according to the present invention.

In Figure 1, 1a1 is a register file, 102 is a multiplexer, 1a3 is a mask register, 104 is a priority encoder, 10S is a decoder, 106 is a zero detection circuit, and 107 is an internal bus. Holds registers visible to software inside the device.

The multiplexer 102 selects the address of the register file 101 from the mask register 1 and the mask register 103.
holds data from the internal bus 107 and holds mask data for save/restore.

Priority encoder 104 is mask register 10
Mask register 10 holds the data supplied from 3.
Each bit is scanned from the right or left end of 3, and the first bit number found and whose 9-bit value is %1# is output. This bit number is used as one input of multiplexer 102. The decoder 10g decodes the output code of the priority encoder 104, and specifies the bit position to be cleared when the contents of the mask register 103 are specified by the firmware.

Zero detection circuit 106 examines the contents of mask register 103 and outputs whether or not it is zero.

Next, circuit operation will be explained with reference to an actual example of register saving.

First, the firmware loads the save mask data into the mask register 103, and then the 1+! ! Mouth detection circuit 10
Examine the output of B. If the contents of the mask register 103 are zero, the process ends. If it is not zero, the priority encoder 104 is outputting the address of the register to be saved, so select this address to be the output of the multiplexer 102, read the contents of the register file 101, and save it to the main memory 1. at the same time,
The decoder 105 corresponds to the contents of the selected register f
The bit in the mask register 103 to be used is specified, and this bit is cleared in the next cycle. Therefore, in the next cycle, the register address to be saved next is obtained from the output of the priority encoder 104.

In this manner, the firmware processing loop is executed until the output of the zero detection circuit 106 becomes true.

(Effects of the Invention) As explained above, the present invention uses a priority encoder to determine the register address to be saved/restored next, so that the processing cycle required is only the number of times the contents of the register to be saved are read. However, this has the effect of speeding up the save/restore process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a save/restore register address generation circuit according to the present invention. . FIG. 2 is a block diagram showing an example of a save/restore register address generation circuit according to the prior art.
01...Register file 102.202...Multiplexer 103, fist, mask register 104...Priority engoder 105-...Decoder 106...Zero detection circuit 10F...Internal path 203...Address Counter 204--Incrementer/Decrementer 20S...
Conflict work register 206...Shifter 20F...Test condition multiplexer Figure 1

Claims (1)

[Claims] a mask register for holding a word that selects a register to be saved/restored from the register file;
a priority encoder for checking the contents of the mask register, scanning from the right end or the left end, and outputting the number of the position where the first bit value found is "1"; and the mask register according to the output of the priority encoder. A save/restore register address generation circuit comprising a decoder for clearing the contents of a register and a zero detection circuit for detecting that the contents of the target register are zero. .