JPH02133841A - Data store control system - Google Patents

Abstract

PURPOSE:To improve the processing efficiency by changing the partial write data into the full write data to a main storage device with an instruction which performs the data reading/writing jobs to the main storage device in the same flow. CONSTITUTION:The contents of a store data register 7 holding the calculated result of a computing element are stored and aligned. This stored and aligned value is merged with the value of a BS read data register 13 via a merging circuit 9, and this merged result is set into an MS store data register 14. The data stored in the register 14 is turned into the full write data and written directly into a main storage device with addition of a check bit. Thus it is possible to change the partial write data set with an instruction which performs the reading/writing jobs in the same process flow into the full write data. Then the busy state of the main storage device is reduced and therefore the instruction processing efficiency is improved.

Description

[Detailed Description of the Invention] [Summary] A data store control method for a main memory device writes data of fewer bytes than the above data width to a main memory device that performs reading/writing with a data width of multiple bytes. Conventionally, in the case of partial writing to
The purpose of this method is to read and write data in the same processing flow, with the aim of solving the problem of reading data with a predetermined byte width, merging it with write data, converting it to data with a predetermined byte width, and writing it. In the case of an instruction that performs an operation, a register having a byte width of write data to the main memory or a byte width of an integer multiple thereof, and a circuit for merging the contents of the register and the arithmetic weak output are provided, and the main memory is The configuration is configured to convert partial write data to full write data.

[Industrial application field]

The present invention relates to a data store control method for main memory in a computer system using pipeline control, and in particular, data store control for instructions that read and write data to the main memory in the same processing flow. Regarding the method.

[Prior Art] Data is stored in the main memory using check pits added to the data.
g and correction), n(2
Larger integer) Data is often read/written in byte units, and for boat fishing, a check pit is added to data in 8-byte units.

In this case, if the data to be written to the main memory is 8 bytes wide, you can just write the data to the main memory as is, but if you want to write data with a data width smaller than 8 bytes To do this, first read data in 8-byte width from main memory, merge it with the write data, add check pit again, and write data in 8-byte width to main memory. There is a need.

In this way, in the case of a so-called partial write request in which data with a data width smaller than 8 bytes is written to the main memory,
- It becomes necessary to read data from the main memory, but depending on the type of instruction, there are some that require reading data from the main memory first in order to process the instruction. After that, if a partial write request occurs, it is necessary to read, merge, and store the data in 8-byte units from the main memory again, and the data is read from the main memory twice in 8-byte units. Data is being read.

A specific example will be described below.

FIG. 3 is a diagram showing the processing flow of an instruction for reading and writing data to the main memory in the same flow as in the conventional example, and shows the processing flow of an instruction for reading and writing data to the main memory in the same flow as in the conventional example.
This is an example of processing an "AND Immediate" command that takes the AND of data and a numerical value, and an example of reading and writing data to the main memory in the same processing flow. be.

The operation will be explained below based on FIG.

Period division symbols in the diagram: D, A, B, ElW.

S represents the state of each process in the pipeline process, 51 represents the instruction to be executed and the classification of each pit that constitutes the instruction, and 51a represents the operation: l-)' (OP
), 51bit immediate value instruction (D immediate value (L), 51c
is the register specification pit (B,
), 51d represents a relative address part (D, ).

First, in the D-state, the instruction is decoded and the register in the general-purpose register group (GR) 52 indexed by the register designation bit (B,) in the instruction 51 (hereinafter simply 'GR(Bl))
(also referred to as J) reads the contents.

Subsequently, the content of GR (B,) read in the A-state and the value of the relative address section (D+) 51d in the instruction 51 are added by the address adder 53, and the added value is stored in the buffer storage section (BS). 54 in the address register.

The data in the buffer storage N (BS) 54 is read out in the B-state, and the data is aligned.
nt) and set it in the arithmetic unit input register 55.

In the E-state, the arithmetic unit 56 performs an operation (for example, 1-byte AND, etc.) on the data read from the buffer storage unit (BS) 54 and the immediate value (I,) in the instruction 51, and the result is stored in the store data register 57. Set to .

In the W-state, the calculation results are stored and aligned to create data to be written to the buffer storage unit (BS) 54 and the main memory, and in the S-state, the data is written to the buffer storage unit (BS) 58, and Data is sent to the main memory (signal line indicated by 59 in the figure).

According to the procedure described above, instructions for reading and writing data are processed in the same flow.

Since writing such data is 1 byte, it becomes a partial write request to the main storage device.

Therefore, when writing the above data in main memory,
It becomes necessary to read, merge, and write data in units of 8 bytes again.

Next, FIG. 4 shows an example of a circuit configuration of a conventional data store control method.

In this figure, only the portions related to data transmission to the buffer storage unit (BS) and main memory are shown.

The address calculated in the A-state is set in the BS address register 61 via the address selector 60.

Data read from the buffer storage unit (BS) in the B-state (when there is corresponding data in BS, that is, when BS is hit) is set in the BS read data register 64 via the fetch align circuit 63. .

If there is no corresponding data in the buffer storage (BS) 54, the data fetched from the main memory is fetched and aligned via the data selector 62 and set in the read data register 64.

In the E state, the value of the BS read data register 64 and the immediate value (Ia) 51b of the instruction 51 are operated on by the arithmetic unit 56, and the result of the operation is set in the store data register 57.

BS via the store align circuit 65 in the W-state.
The data of the operation result is set in the write data register 66 and the MS store data register 67, and in the next S state, writing is performed in the buffer storage unit (BS) 54, and partial write data is sent to the main storage device. Ru.

At this time, the address is set in the BS address register 61 in the B-state, and in the E-state and W-state.
They are set to the BS address #E register 68 and the BS address #W register 69, respectively, and then set to the MS-store data address register 70 in the S-state, synchronizing with the write data as the store data address to the main memory. Sent.

[Problem to be solved by the invention]

As explained above, in the conventional method, the immediate value instruction (A
When executing a program such as ND Immediate, data is first read from the main memory in 8-byte units for data processing, and in response to a partial write request that occurs after processing the data, the data is read from the main memory. Then, it is necessary to read, merge, and write data in 8-byte units again.

Therefore, when performing the above-mentioned partial write, it takes an extra amount of time to read the data from the main memory, compared to when simply writing 8 bytes of data.

Furthermore, especially when there are consecutive immediate instructions (AND Immediate instructions), that is, when the write data to the main memory is a series of partial write requests, the bank of the main memory is often in a busy state. , subsequent instructions often require a request to store or fetch data from the main memory.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a data store control method that improves the processing efficiency of instructions for reading and writing data to and from a main storage device in the same processing flow. purpose.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims.

That is, the present invention is a computer system that operates in a pipeline, and in a data store control method in which data is read from and written to a main memory in the computer system in a plurality of byte widths. One or more registers having a byte width of data or an integral multiple of the byte width and a merging circuit for merging the contents of the register and the output of the arithmetic unit are provided, and the main memory is stored in the same processing flow. , when executing an instruction to read and write data, the read data from the buffer storage unit or main memory is specified to the register, and the operation result, which is the output of the arithmetic unit, is partially written to the register. This is a data store control method that converts partial write data to the main storage device or buffer storage unit into full write data.

[Function] Reading and writing of data to the main memory is usually performed in units of n bytes due to check pits, and for boat fishing, for example, check pits are often added in units of 8 bytes. .

In such cases, conventionally, when writing data with a data width smaller than 8 bytes, the data was first read in 8-byte units from the main memory, merged with the data to be written, and then check pits were added. The data is converted into 8-byte data and then stored in the main memory.

By the way, some instructions to be processed read and write data to and from the main memory in the same processing flow. Since data is being read, if there is a need for partial writing with the instruction, the read data is set in a register, a merge circuit is used, and the operation result, which is the arithmetic unit output, is transferred to the register. By performing a partial write to the main memory, the partial write data to the main memory is converted in advance to full write data with a data width of 8 bytes and sent to the main memory, which was previously necessary for a partial write. Reading data from the main memory can be omitted.

[Example] FIG. 1 shows the instruction processing flow of the data store control method for the main memory of the present invention, and 1 indicates the instruction to be executed.
and the classification of each pit composing the instruction, la is the operation code (OP), and lb is the immediate value (■,
), 1c is the register specification pin (Bl) of the general-purpose register group (GR), 1d is the relative address section (Dl), 2 is the general-purpose register group (GR), 3 is the address adder, and 4 is the buffer storage section (BS). ), 5 is the BS read data register,
6 is an arithmetic unit, 7 is a store data register, 8 is a buffer memory aB (BS), 9 is a merge circuit, 10 is a BS address register, 11 is a fetch align circuit, 12 is a BS read data register #E, 13 is a BS read Data register #W, 14 is MS store data register, 1
5 is BS store address register #E, 16 is BS store address register #W, 17 is MS store data address register, 18 is store align circuit, 19 is BS
Write data registers 20 to 24 represent each register.

The difference between the processing flow shown in FIG. 1 and the processing flow shown in FIG. This is to be set in the MS store data register 14.

That is, in the conventional method, data is stored in the main memory by partial writing, but in the case of the present invention, data is stored in the main memory by partial writing.
The data in the S store data register 14 is assumed to be 8-byte wide write data, and a check pit is added thereto, and then written to the main memory.

FIG. 2 is a diagram showing an example of a circuit configuration of a data store control method for a main memory device according to the present invention, in which reference numeral 25 denotes an MS fetch data register that holds data read from the main memory device;
Reference numeral 26 represents a data selector for selecting read data from the buffer storage unit (BS) or the main memory, and 27 represents an address selector, and other symbols are the same as in FIG. 1.

This example will be explained below.

The address calculated in the A-state is set in the BS address register 10 via the address selector 27.

Data read from the buffer storage unit (BS) 4 in the B-state and passed through the fetch align circuit 11 is set in the BS read data register 5.

At this time, the buffer storage unit (BS) 4 selected by the data selector 26 does not pass through the fetch align circuit 11.
Either BS read data, which is data read from the main memory, or MS fetch data, which is data read from the main memory, is BS! It is set in the J-code data register #E12.

In the next E-state, the calculated result is set to the store data register, and the contents of the BS read data register #E12 are set to the BS read data register #E12.
Moved to W13.

In the W-state, the contents of the store data register that holds the calculation results of the arithmetic unit are stored and set to the BS write register 19, and the stored value and the value of the BS read data register #W13 are transferred to the merge circuit 9. and set the result to the MS store data register 14.

In the next S-state, the value of the BS write data register 19 is written to the buffer storage section (BS) 4, and the value of the MS store data register 14 is sent to the main memory as store data.

In this case, the MS store data is not a partial write, but an 8
All written data is byte wide.

As a result, partial write data in an instruction for reading and writing in the same processing flow can be replaced with full write data, and the busyness in the main storage device can be reduced.

In addition, all merged write data is stored in the buffer storage section (B
There is no problem at all with writing data to S).

Furthermore, the present invention can be applied not only to writing data to the main memory but also to writing data to the pre-buffer storage (BS).

Furthermore, even if an instruction, such as a store instruction, does not normally require reading from the BS or main memory, in the case of a partial write, reading data from the main memory or BS is
By performing this in a state, it is possible to read and write instructions in the same processing flow, and the present invention can be applied thereto.

[Effects of the Invention] According to the present invention, in the case of an instruction to read and write data to the main memory in the same flow, partial write data to the main memory can be changed to full write data, The busy state in the main storage device is reduced and processing efficiency is improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the instruction processing flow of the data store control method of the present invention. FIG. 2 is a diagram showing an example of the circuit configuration of the data store control method of the present invention. FIG. 3 is a diagram showing an instruction processing flow of a conventional data store control method. FIG. 4 is a diagram showing an example of a circuit configuration of a conventional data store control method. 1...Instruction to be executed and classification of each bit constituting the instruction, 1a...Operation code (OP), lb...Immediate value (I, )
, 1c...Register designation bit (Bl) of general register group (GR), ld...Relative address part (D,), 2...General purpose register group (GR) ,
3... Address adder, 4... Buffer storage section (BS), 5... BS read data register, 6... Arithmetic unit, 7... ...Store data register, 8...Buffer storage section (B
S), 9...Merge circuit, 10...
BS address register, 11...Fetch align circuit, 12...BS read data register #E113...BS read data register #W
, 14-...MS store data register, 15
...BS store address register #E16...
...BS store address register #WS17...
...MS store data address register, 18...
...Store align circuit, 19...BS write data register, 20 to 24...Each register, 25...MS fetch data register, 26
...Data store, 27...Address selector

Claims (1)

[Claims] In a computer system that operates in a pipeline, in a data store control method in which data is read from and written to a main memory in the computer system in a plurality of byte widths, One or more registers having a byte width of the write data or an integral multiple thereof, and a merging circuit for merging the contents of the register and the output of the arithmetic unit are provided, and the data is stored in the main memory in the same processing flow. On the other hand, when executing an instruction to read and write data, set the read data from the buffer storage unit or main memory to the register, and partially write the operation result, which is the output of the arithmetic unit, to the register. A data store control method characterized in that partial write data to a main storage device or a buffer storage unit is converted into full write data.