JPS6168636A - Data processor - Google Patents

Abstract

PURPOSE:To check a tag part at a high speed by providing a storage part with storage parts for a tag and a value, storing tap parts of plural data in the same addresses of a tag storage part and their values in respective addresses of the value storage part, and reading plural tags at the same time. CONSTITUTION:The storage part 12 is provided with the tag storage part 12A and value storage part 12B for data and the address of the storage part 12B consists of (a) bits; and its high-order a-b bits indicate the address of the storage part 12A and the (b) bits indicate a position in the address. Then, the storage part 12B is stored with one data in a storage area accessed with one address and the storage part 12A is stored with plural data respectively. Further, a processing part 10 sets an address in an address register 22 to read the storage part 12B with its all bits and the storage part 12A with the high-order a-b bits, and when only the tag part is read out, only the storage part 12A is read with the high-order a-b bits.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device, and attempts to perform operations such as data type determination at high speed by collectively storing tag portions of data. It is something.

[Conventional technology]

Some data has a tag part that stores information (tag) indicating the type of data. The type of data is integer, decimal, etc., and LISP
There are many types of data in languages. Considering an operation such as addition, the processing procedure is different depending on whether the multiple data to be added are all integers or some are decimals, such as floating point numbers, and the program to be run is different. For example, if all the numbers are integers, the addition process can be started immediately, but if floating point numbers are mixed in, the integers must also be converted to floating point numbers to make them all the same floating point numbers. In such a case, it is necessary to check the types of all data to be operated on, and decide which processing program to run based on the results.

[Problem that the invention seeks to solve]

Conventionally, in order to determine the type of a plurality of pieces of data (data of a plurality of words), the memory is accessed as many times as the number of words, the plurality of pieces of data are read out, and the type is determined from the tag section. This method requires a large number of accesses and is time consuming, and because only a small portion of the read data is actually used for determination, there is a lot of waste.

The present invention aims to improve these points, to quickly check the tag portions of a large number of data, and to efficiently and quickly perform type determination.

[Means for solving problems]

The present invention provides an apparatus that includes a processing section and a storage section and processes data having a tag, in which the storage section is provided with a tag storage section and a value storage section, and when the data is stored in the storage section, a plurality of pieces of the data are stored. The tag parts of the plural pieces of data are stored together at the same address in the tag storage part, and the value parts of the plural pieces of data are individually stored in each address of the value storage part. This is characterized in that a plurality of tags are simultaneously read out from the tag storage section.

To explain with drawings, FIG. 1 shows an outline of a data processing device, in which 10 is a processing unit (processor), 12 is a storage unit, and 14 is a data processing device.
．． 16 is an output circuit, 18 is a write register, 20 is a read register, and 22 is an address register. The storage unit 12 is a stack or the like, and the data tag storage unit 1
2A and a value storage section 12B. FIG. 2 shows a'("details") of the storage unit 12, and as shown in the figure, one data value is stored in the storage area accessed by one address in the value storage unit 12B, and multiple data values are stored in the tag storage unit 12A. That is, n data tags called data mill data (i+n-1) are stored.Storing of such data tags and values is performed using the upper a-b of the address of the value storage section 12A, assuming that the address consists of a bits. This can be implemented by using bits to represent the address of the tag storage unit 12A and b bits representing the position within the address. Note that b has a relationship of 2 zn here.

To read the data in the storage section 12 in its original data form (tag+value), set an address in the address register, read out the value storage section 12B with all bits of that address, and It is sufficient to read out the tag storage section 12A using the -b bit, select the readout output of the tag storage section 12A using the lower b bits, and connect it with the readout output of the value storage section 12B. In addition, when reading only the data tag section from the storage section 12, it is sufficient to read out the tag storage section 12A using the high-order a-b bits of the address of the register 22. As a result, n tags are read out for each access, and the data It is possible to check the data type of a group at high speed.

Writing is done by grouping n (fixed data tags together as a word),
Each value of these data is 1 word, and the register 22
The value storage unit 12B is accessed using all bits and nodes of the address set in the register 22, and the above value is written to each address, and the tag storage unit is accessed using the upper a-b bits of the address set in the register 22 to write the value. 1 for each n access to the value storage unit 12B when n tags are added to the address at the same time.
It can be executed by writing at a rate of 1. Of course, these reading and writing procedures can be changed as appropriate.

FIG. 3 shows an example of the output circuit 16 and its peripheral circuits when the word length is 16 bits, the tag part is 4 pints, and the value part is 12 bits. The readout output of the value storage 1.2B, ie, the 12-bit data value part, is led to the multiplexer 16e via the register 16b, and the readout output of the tag storage 16a, ie, the four 4-bit tags, is led to the multiplexer 16e via the register 16a. Each of the 4 bits are routed to multiplexer 16c, the first 4 bits +-0 to 3 are routed to multiplexer 16d, and the latter 12 bits 4 to I5 are routed to multiplexer 16e.

Multiplexer 16c is selected by signal S1. The signal S1 is the lower b bits of the access address set in the address register 22, and in this example, 00.
Of, 10.11. Therefore, this signal causes one of the four tags (0-3, 4-7, 8-11, 12-
15) can be selected. The signal S2 is a selection signal that is at a high level or a low level depending on whether it is a normal continuous readout or a continuous tag readout.
outputs tags O to 3, and outputs tags 4 to 15 to multiplexer 16e. Therefore, the successive register 20
is 41 tags 0-3, 4-7.8-11.12-15
is input, and thus tag reading is performed quickly in units of 4iVA. If the signal S2 indicates normal readout, the multiplexer 16 (i is the tag O to 3 from the multiplexer 16c)
．． 4-7, 8-11, 12-15, and multiplexer 16e outputs the data value from register 16b, so read register 20 outputs 16-bit data in the form (tag+value). do.

〔Effect of the invention〕

As described above, according to the present invention, since a plurality of data tag sections can be accessed at once, operations such as type determination of a plurality of data can be performed at high speed, which is extremely effective.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a diagram explaining the state in which data is stored in the storage section, and Fig. 3 shows data in 16 bits/word and tag part in 4 bits. FIG. 3 is a block diagram showing circuits around the output circuit in the case of the above. In the drawing, 12 is a storage section, 18 is a write register, 20 is a read register, and 22 is an address register.

Claims (1)

[Claims] An apparatus that includes a processing section and a storage section and processes data having tags, wherein the storage section is provided with a tag storage section and a value storage section, and when the data is stored in the storage section, a plurality of tags are stored. The tag portions of the data are stored together at the same address in the tag storage section, and the value portions of the plurality of data are individually stored at each address in the value storage section, and each data type of the plurality of data is determined. A data processing device characterized in that a plurality of tags are simultaneously read out from a tag storage section.