JPS62156742A - Data writing control system - Google Patents

Abstract

PURPOSE:To evade such a case where a part that must not be rewritten is finally changed by reading out the immediately preceding data on a register to which a write mode is designated to store this data and then synthesizing the read-out data with the write data to write them into a register. CONSTITUTION:A register file 501 consists of 32 registers 600-631 having the 32-bit width respectively. The input of each register is connected to a double input multiplexer 502 of 32 bits. then the output of the multiplexer 502 is written with write signals 632-633. The output of each register is connected to a data bus 504 via output buffers 700-731 and read out to the bus 504 with read signals 732-763. The multiplexer 502 is connected between the file 501 and the bus 504 and synthesizes the output of a blocking register 503 with the whole or a part of 32 bits of the bus 504. Then the multiplexer 502 synthesizes the contents of the register 503 and the bus 504 in various ways by the value of the control input 511.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data writing control method for a register in a data processing device that processes data of a plurality of different bit lengths.

[Conventional technology]

In a data processing device, the length of data handled is not necessarily limited to one type. For example, when dealing with English character codes or short integers, a length of at most 8 bits is sufficient (hereinafter data with a length of 8 bits is referred to as byte data); When handling integers, data with a length of 16 bits is called half-word data). Furthermore, when handling larger integers or floating point numbers, a length of 32 bits or more is required (hereinafter data having a length of 32 bits will be referred to as word data).

This correspondence between data behavior and data bit length is called a data type.

FIG. 3 shows the configuration of a typical data processing device.

Data is usually stored in the storage device 101 or the central processing unit (
102 (hereinafter referred to as a processor). Data placed in the storage device 101 is once taken into the register 104 and then subjected to processing such as calculation and transfer.

Generally, a single register can store data belonging to a plurality of different data types. For example, a register with a width of 32 bits is
) and (C), byte data 201, half word data 202 and word data 20
The positions of the least presence/absence bits (LSBs) are aligned so that 3 can be stored.

Furthermore, one register is not necessarily used for the same data type during execution of a certain program. At some times it may be used as a byte type and at other times as a word type. For example, the length of the register for word data is long enough to store four bytes of data. For this reason, registers are often used to store data of multiple shorter data types. FIGS. 5A and 5B show how four byte data and two half word data are stored in a 32-bit wide register.

As mentioned above, when storing multiple pieces of data in one register, only one of the multiple pieces of data is rewritten.If you do not change only the part that corresponds to the data type, other data parts in the register will be affected. is also rewritten at the same time,
Data in registers unrelated to transfer cannot be guaranteed.

To avoid the above-mentioned disadvantages, it is common to change only the necessary range of bits depending on the specified data type when writing to a register. The function of changing only a series of bit strings of data in this way is called a partial write function.

FIG. 6 shows a conventional example of a 32-bit register having a partial write function for the lower 8.16 or 32 bits depending on the data type.

A 32-bit register 401 is connected to a data path 403 via a 32-bit data buffer 402.
The contents are output by the read signal 414. Also, write signal 410 writes only the lower 8 bits (bit numbers 0 to 7) of the data bus, 411 writes the next lower 8 bits (bit numbers 8 to 15), and 412 writes the upper 1 bits.
This is a signal for rewriting 6 bits (bit numbers 16 to 31).

The 2-bit signal 415 indicating the type of data type indicates the bit width to be transferred to the register.
b indicates a binary number) represents byte data, 0
1b means transferring half word data, and 10b means transferring word data. Also, pledge signal 413
is a control signal that specifies writing data to this register.

When the write signal 413 becomes active, the write control circuit 404 sets only 410 to 1 if the data type signal 415 is oob, and sets 410 and 411 to 1 if the data type signal 415 is 01b.
If it is 0b, all 410, 411 and 412 are controlled to be active.

In the conventional example described above, three write signals (410, 411 and 412) are sent to one register in order to write data belonging to the 3ffi data type.
Moreover, a unique write control circuit 404 is required.

As the number of registers increases and the variety of data types increases, the aforementioned control signals and control circuits also increase proportionally.

When a register with a partial write function is mounted on a printed circuit board using an IC package, the number of control signals is large and the amount of wiring is significantly increased compared to configuring the same amount of registers without a partial write function. However, due to the complexity of the configuration of a single register and the limited number of pins of an IC package, many packages are required, which increases the mounting area.

Furthermore, even when implementing a register with a partial write function in an LSI, compared to a register without a partial write function, the mask pattern (having the function of configuring each bit of the register) that constitutes a unit register ( The geometrical arrangement (which determines the transistors and wiring within the LSI) becomes complex, and the mounting area of the register increases because extra control signals cross within the mask pattern.

[Problem that the invention seeks to solve]

In view of the drawbacks of the conventional example, the present invention provides a partial write function using a register capable of writing data of one type of bit width in a data processing device having a register that stores data belonging to a plurality of data types. It is an object.

[Failure to solve the problem]

The present invention has a plurality of registers that store data of different bit lengths, and when writing data shorter than the bit length of the register, the data is processed without changing the contents of bits other than the designated bits. The writing method includes means for holding the contents of a designated register, and means for combining the data to be written with the held data, reads the contents of the designated register, and combines the written data with the holding means. It is characterized in that data obtained by combining data held in the register is written back to the specified register.

[Function/principle of the invention]

When writing data to a register, read and store the data immediately before the register specified for writing, and after combining the stored data and the write data (blocking), write to the specified register. This ensures that the portion of the register designated for writing that must not be rewritten will not change as a result.

〔Example〕

Hereinafter, the configuration and operation of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

Register file 501 is comprised of 32 32-bit wide registers 600-631. The input of each register is connected to a 32-bit two-way multiplexer 502, and the contents of the output of multiplexer 502 are written by write signals 632-663 to each register. On the other hand, the output of each register is connected to a 32-bit data bus 504 via an output buffer 700-731 of each register, and read onto the data bus 504 by read signals 732-763 for each register.

The blocking register 503 is connected to the data bus 504, and when transferring the contents of the data bus 504 (destination data) to the destination operand register 505 to the ALU, the blocking register 503 sends a write-in signal 51 to the destination operand register 505.
2 is a 32-bit latch that latches the contents of the data bus.

A multiplexer 502 is connected between the input of the register file 501 and the data bus 504, and has the function of combining the output of the blocking register 503 with all or part of the 32 bits of the data bus 504. The multiplexer 502 also has a 2-bit control input 511, and according to the value of the control input 511, the contents of the blocking register 503 and the contents of the data bus 504 are combined as follows.

(2) When the control input is oobO, the data written from the data bus is 8 bits, indicating that the upper 24 bits of the register must not change. The lower 8 bits of the data bus 504 are selected for the lower 8 bits of the output, and the upper 24 bits of the contents of the blocking register 503 are selected for the higher 24 bits of the output.

- When the control input is Olb, the data written to the data bus is 16 bits, indicating that the upper 16 bits of the register must not change. The lower 16 bits of the output contain data.
The lower 16 bits of the bus 504 are selected, and the upper 16 bits of the contents of the blocking register 503 are selected as the upper 16 bits of the output.

- When the control input is 10b, the data written from the data bus is 32 bits, indicating that the contents of the register change in all 32 bits. The 32 bits of output require a data bus 50
4032 bits are output up to 7.

The ALTJ'507 is a 32-bit arithmetic logic unit that performs arithmetic operations such as addition on the contents of the source operand register 506 and destination operand register 505 connected to the data bus. Operation designation signal 514 for logical operations such as AND
Follow the instructions. The calculation result is sent via a 32-bit output pin 508 connected to the data bus.
When read signal 515 becomes active, data bus 5
04.

Source operand register 506 and destination operand register 505 are both 32-bit registers connected to data bus 504 and
Temporarily holds data for two-operand operation in U507. Write signals 512 and 513 are write signals for destination operand register 505 and source operand register 506, respectively.

Generally, a two-operand arithmetic instruction is executed as follows.

■ Register 60 specified as source operand
The contents of 0-631 are transferred to source operand register 506 via data bus 504.

■ The contents of registers 600 to 631 designated as destination operands are transferred to destination/operand register 5 via data bus 504.
05 and the blocking register 50.
Transfer to 3.

■ AL for the contents of source operand register 506 and destination operand 505.
Calculation is performed in U507.

(2) Transfer the operation result from the output buffer 508 of the ALU to the data bus 504;

(2) According to the contents of the control input signal 511, the contents of the data bus 504 and the contents of the blocking register 503 are combined and written to registers 600 to 631 designated as destination operands.

Next, the operation will be explained using an example. Now register 6
Assume that 66666666h is stored in the register 615 (h indicates a decimal number). The command is ADDBRO, R, 1
Assume that you want to execute 5. This instruction means to add 8-bit data stored in register 600 and 8-bit data stored in register 615, and transfer the obtained result to register 15 (615).

For both registers 600 and 615, the data involved in addition is only the lower 8 bits (600 is 78h, 1615 is 66h), so the final content of register 600 is 123456DEh (78h+66h=ODEh).
) is obtained (see FIG. 7(A)).

Now, first, the contents 66666666h of register 615 are
Transferred to source operand register 506 via data bus 504.

Next, the contents 12345678h of register 600 are transferred to destination operand register 505 via data bus 504 and transferred to blocking register 503. Since ALU 507 always performs calculations in 32-bit width, ALU5
The output of 07 is 789ABCDEh (12345
678h+66666666h) is obtained.

The calculation result (7s9ABc[h) is the data bus 504
The multiplexer 502 is reached via the . Since the byte type is specified as the data type (the control input 511 is 00h), the lower 8 bits of the output of the multiplexer 502 are the lower 8 bits of the data bus 504, that is, 0DEh, and the upper 24 outputs of the multiplexer 502 are the lower 8 bits of the data bus 504.
The bits include the upper 24 bits of the blocking register 503, that is, the destination operand register 505 as the destination operand first.
Top 24 pics of 12345678h transferred to) 12
3456h is output. Therefore, the entire output of multiplexer 502 consists of 32-bit data of 123456DEh, and this value is stored in register 60.
Written to 0.

Similarly, when handling 7-word data, use the addition instruction ADDHW for 7-word data instead of the above-mentioned ADDB instruction. This is when R15 is executed.

In this case as well, the calculation result (789ABCDEf) is the data
Until it is output to bus 504, it is the same as for the byte data type. Half as data type
Word type is specified (control force 511 is 0)
1h), the lower 16 bits of the output of the multiplexer 502 contain the lower 16 bits of the data bus 504, that is, 0.
The upper 16 bits of the output of the multiplexer 502 are the upper 16 bits of the blocking register 503, and the upper 16 bits of the blocking register 503 are
i.e., first register 50 as the destination operand.
Upper 16 bits of 12345678h transferred to 5) 1
234h is output. Therefore, multiplexer 5
The overall output of 02 is 3, which is 1234BCDEh.
2-bit data is configured and this value is stored in register 600.
(see FIG. 7(B)).

In addition, if you want to handle word data, use the ADD mentioned above.
Addition instruction AD for word data instead of B instruction
This is when DW RO, R15 is executed. In this case as well, the calculation result (789ABCDEf) is transferred to data bus 50.
4 is the same as the case of the word (item) data type. Since the word type is specified as the data type (the control input 511 is 10h), the 32-bit output of the multiplexer 502 is consists of 32 bits of data bus 504, ie 32 bits of data 789ABCDEh, and this value is stored in register 6.
00 (see FIG. 7(C)).

FIG. 2 is a diagram showing another embodiment of the present invention. In this embodiment, the input of register file 501 is routed directly to data bus 50 without going through multiplexer 502.
A 32-bit multiplexer 502 is connected between the output of the ALU 507 and the data bus 508. be done.

As a substitute for the blocking register 503, here a destination operand register 505 is used.
Use. The output of destination operand register 505 is connected as an input to ALU 507 as well as the other input to multiplexer 502.

The multiplexer 502 has a 2-bit control input 511 as in the previous embodiment, and this value controls the contents of the destination operand register 505 and the ALU 50.
The outputs of 7 are combined as follows.

■ When the control input is oobO, the upper 24 bits of the register must not change. The lower 8 bits of the output are the lower 8 bits of the ALU 507, and the upper 24 bits of the output are the upper 2 of the contents of the destination operand register 505.
Select 4 bits.

■ When the control input is oibO, the upper 16 bits of the register must not change. The lower 16 bits of the output contain the ALU507
The lower 16 bits of the output are selected, and the upper 16 bits of the contents of the destination operand register 505 are selected as the upper 16 dots of the output.

■ When the control input is 10b, the contents of the register indicate that all 32 bits are changed. The 32 bits of the ALU 507 are output as they are as the 32 bits of output.

In this embodiment, since the blocking register 503 is not required in contrast to the previous embodiment, it is not possible to simplify the hardware, but to use register resources connected to the data bus 504 other than the register file 501. Also for
It becomes possible to provide a partial write function.

In two-operand operations such as addition, subtraction, AND, and OR instructions, the source and destination operands are always transferred to the ALU.
No extra transfers are required to combine destination data and operation results.

On the other hand, in one-operand operations for implementing logical negation, two's complement instructions, etc., only the destination operand is normally transferred to the ALU, so there is no waste in transferring data for data synthesis.

By the way, for instructions that do not perform operations in the ALU, such as instructions for transferring data between registers, there is no need to read the destination operand.
The partial write function can be implemented by transferring the contents of the destination operand to the blocking register for data synthesis, or by performing a pseudo operation by specifying ALU operation operation - no operation (NOP). It can be realized.

Furthermore, it is clear that for instructions that are complex to execute, these transfers represent a negligible overhead in terms of overall processing.

〔Effect of the invention〕

As explained above, the register partial write function can be realized using a register that only has a single word length write function, so registers in a processor that handles data belonging to multiple data types can be Since it can be realized with less hardware and less amount of wiring, high-density packaging is possible. Furthermore, since LSIs can be realized in a small area, the area of the entire chip can be reduced, LSIs can be manufactured at low cost, and other useful functions can be realized within the same area.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of one embodiment of a processor using the present invention, FIG. 2 is a diagram showing the configuration of another embodiment of the processor using the present invention, and FIG. 3 is a diagram showing typical information. FIG. 4 is a drawing showing the configuration of the processing device; FIG. 4 is a drawing showing the storage format of data belonging to various data types in the registers (A);
is byte type, (B) is half word type,
(C) shows the word type, and FIG. 5 shows how multiple data are stored in one register. (A) shows 4 byte data and (B) shows 2 half word data. FIG. 6 shows the structure of a register with a partial write function corresponding to multiple data types, and FIG.
The figure is a detailed explanation drawing of the present invention. 101... Storage device, 102... Central processing unit, 103... Bus, 104...
・Register, 201...Hide data, 20
2...Half word data, 203...
...Word data, 301-304...Byte 7 1', 311-312...Half word data, 401...32-bit register, 402 ...32-bit output buffer 77,
403...32-bit data bus, 404
...Write control circuit, 404...Write control circuit, 410...Write signal for lower 8 bits, 411...Write signal for middle 8 bits,
412...Write signal for upper 16 bits, 41
3... Input control signal, 414... Read control signal, 415... Data type designation signal, 501... Register file, 502
...32-bit multiplexer, 503...
...Blocking register, 504...
32-bit data bus, 505...Destination φ operand register, 506...
...Source operand register, 507...
・32-bit ALU, 508... Output output buffer 11 for ALU... Data type designation signal, 512... Destination operand register write signal, 513... ...Source operand register write signal, 514...A
LU operation designation signal, 515...ALU operation result read signal, 600-631...32 bits.
Register, 632-663...Register write signal, 700-731...Register output buffer, 732-763...Register read signal/' 4 times 31 2423 16/S, 517
0th s12] Fig. 6 1234BCDE Fig. 7 (A) (C)

Claims (1)

[Claims] A method of writing data without changing the contents of bits other than the specified bits when writing data shorter than the bit length of the register with multiple registers storing data of different bit lengths. and a means for combining the data to be written with the held data, reads the contents of the specified register, and combines the written data and the data held in the holding means. A data write control method characterized in that the data written in the data is written back to the specified register.