JPH0658629B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer processing system, and more particularly to a data processing apparatus having an instruction decoding system suitable for a microcomputer of a micro program control system.

[Background of the Invention]

In the field of microcomputers, the complexity of logic arises with higher integration, so that a method of realizing an integrated circuit by a logic circuit having a regular structure is becoming mainstream. One of them is a micro program control method. As a data processing device of the micro program control system, it is general that it is configured by using an instruction decoder that generates an address of a micro program ROM from an instruction word. A microprogram control system in which this instruction decoder is omitted is described in Japanese Patent Application Laid-Open No. 57-203141. In this system, an instruction word is directly sent to the microprogram R.
Since the number is registered as a part of the address information of the OM, the address length of the microprogram ROM increases with the instruction word length as the word length of the instruction word increases to 8, 16 and 32 bits. Although there is an increase, no particular consideration was given to this point.

[Object of the Invention] An object of the present invention is to provide a data processing device which reads an instruction word stored in a main storage device, decodes the instruction word, and executes the instruction word. To provide.

[Outline of Invention]

In order to achieve the above object, the present invention adopts an instruction decoding method in which a machine instruction word is rearranged into an orthodox intermediate machine language suitable for a hardware configuration and executed.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, and is a block diagram of a single-chip microcomputer 10 constructed on one semiconductor substrate, with a central processing unit 101 serving as a data processing unit serving as a core, and a main storage unit. 102, a peripheral device 103 having a timer function and an input / output function, a direct memory access device 104, and an address translation device 105. Second
The portion of the processor 20 indicated by the broken line in the figure will be described in detail with reference to FIGS.

FIG. 1 is a block diagram of a portion of a processor 20 showing an embodiment of the present invention. The instruction word storage / conversion unit 201,
Micro program storage / control unit 20 having micro program ROM (Read Only Memory) as a main element
2, decoder unit 203, arithmetic unit 204, bus interface unit 205, readable and writable first main memory device 206, readable second main memory device 207, address input / output buffer 20
82, a data input / output buffer 2083, a clock supply / power supply buffer 2084, an address / data clock, and a signal other than the power supply to the processor 20 and the second part.
It is composed of an input / output buffer 2081 of a signal line connecting with other devices 103, 104, 105 and the like in the figure. The operation from instruction fetch to execution will be described with reference to FIG.

(1) Instruction fetch The contents of the program (instruction) fetch register (instruction address register) in the bus interface unit 205 are stored in the first main storage device 206 and the second main storage device 207 in the processor 20 via the bus 212. Is also applied to the address input / output buffer 2082,
It is supplied to the bus 222 outside the processor 20. An instruction word corresponding to this address is applied from the first main memory device 206 or the second main memory device 207 to the bus 213, or via the bus 223 and the data input / output buffer 2083. 213 is applied. The contents of the bus 213 are supplied to the instruction word storage / conversion unit 201.

(2) Command word storage and conversion The command word applied to the command word storage / conversion unit 201 is temporarily stored and decoded, and converted into information to be input to the microprogram storage / control unit 202.

(3) Microinstruction reading In the microprogram storage / control unit 202, the information converted from the instruction word in the instruction word storage / conversion unit 201 is input as necessary via the bus 231 and is input to the bus 232 as a microinstruction string. Output.

(4) Microinstruction decoding Microinstructions are transmitted from the microprogram storage / control unit 202 via the bus 232 to the microinstruction unit 20.
A signal group 233 for directly controlling the arithmetic unit 204 and a signal group 234 for directly controlling the bus interface unit 205 are output.

(5) Calculation Execution The calculation unit 204 performs desired data calculation according to the signal group 233. The bus interface unit 205 controls the timing of data transfer between the processor 20 and other devices and the timing of data transfer within the processor 20 via the bus 211, the input / output buffer 2081, the bus 221, and the signal lines 235 and 236. To do.

On the other hand, the clock and power supplied to the buffer 2084 are supplied to each unit via the signal line 214.

FIG. 3 shows an example of the configuration of the instruction word storage / conversion unit 201, the microprogram storage / control unit 202, the decoder unit 203, and the arithmetic unit 204 of FIG. The instruction word transferred to the instruction word storage / conversion unit 201 via the bus 213 is temporarily stored in the instruction word storage unit 301 which is the instruction word storage unit and transferred to the instruction decoding unit 302 which is the instruction decoding unit.

Here, FIG. 4 shows an example of a typical instruction format of an instruction word read into the instruction word storage unit 301.

(1) Arithmetic instruction The contents of the first operand specified by the first operand code and the contents of the second operand specified by the second operand are operated, and the result is stored in the position of the second operand. The type of operation in the operation code defines the type of operation such as arithmetic operation and logical operation.

(2) Branch instruction When the condition specified by the branch condition in the operation code is satisfied, the operation branches to the program address indicated by the content of the operand specified by the first operand. If the condition is not satisfied, execute the next command.

(3) Bit manipulation instruction The contents of the bit position indicated by the bit number which is the first operand in the second operand designated by the second operand code is tested and the state of the bit is stored. After the test, an operation (clear, set, change, test) indicating the content of the bit by the type of bit operation in the operation code is executed, and stored in the corresponding bit position of the second operand as necessary.

The above instruction words (1), (2), and (3) have functions originally desired to be included in a limited number of bits based on a certain rule, and as a result, the instruction has an orthogonality due to the limitation of the bit length of one instruction. Is systematized as a sacrifice.

In this embodiment shown in FIG. 3, an instruction word read from the instruction word storage unit 301 is decoded by an instruction decoding unit 302, and various information necessary for executing the instruction is stored in an instruction having a complete orthogonal code system (hereinafter, an intermediate instruction). Called machine language). That is, it independently has an operation code that specifies the operation to be executed and an information bit that represents an operand specifier that identifies the location of the main storage device that contains the operand. The converted intermediate machine language is stored in the storage unit 303, and goes to the microprogram storage / control unit 202 and the decoder unit 203. Some of the intermediate machine languages include at least one operand specifier, and all the information indicating whether the operand indicated by the operand specifier is a source operand or a destination operand is expressed in the operation code.
Further, in the information expressing the operation code and the operand designator, each information of the intermediate machine language other than the information 3031 which needs to be decoded by the micro program storage / control unit 202 can be controlled by the micro instruction bus 232. Each decoder 2031 in
There is a one-to-one correspondence with the inputs 2032, 2033, 2034, 2035 (Fig. 3). Decoder unit 203
The control signal group 233 generated by the various decoders inside controls the arithmetic unit 204 and executes desired arithmetic processing indicated by the intermediate machine language.

FIG. 5 shows another embodiment, which is an instruction word storage unit 301.
2 shows an example in which there are two instruction word decoding units for decoding the instruction word temporarily stored in and generating an intermediate machine language.

When the main memory device in which the user program is stored stores the command words represented by two different command systems A and B, that is, even if the binary command codes are the same, the processing content of the command ( When the instruction function) is different, the instruction decoding unit 302 that decodes the instruction word of the instruction system A and the instruction system B
And an instruction decoding unit 502 that decodes the instruction word. The information generated by the instruction decoding unit 302 is sent to the multiplexer 503 via the bus 3021. Similarly, the information generated by the instruction decoding unit 502 is sent to the multiplexer 503 via the bus 5021. The multiplexer 503 is
Bus 302 based on the contents of flip-flop 504
Either the content of 1 or the content of the bus 5021 is selected and stored in the storage unit 303. At this time, the two instruction decoding units 302 and 502 process the instruction even if the binary code of the instruction represented by the instruction code of the instruction system A is different from the binary code of the instruction represented by the instruction code of the instruction system B. If the contents are the same, the exact same intermediate machine language is generated. That is, if the instruction functions are the same even if the instruction systems have different instruction systems, since the information stored in the storage unit 303 is the same, most of the processor 20 controlled by the intermediate machine language has the same information. The hardware 500 (in FIG. 2, indicates the hardware in the processor 20 excluding the instruction word storage / conversion unit 201) can be commonly controlled even if the instruction system is different.

On the other hand, the flip-flop 504 is configured to detect the level of a signal input to a predetermined terminal 505 when the processor 20 is reset by the control circuit 506 serving as control means and set the result. Terminal 5
Reference numeral 05 also serves as the least significant bit terminal of the address bus.

FIG. 6 shows another embodiment of the bus 2 shown in FIG.
A command word when the command word to be read into the command word storage unit 301 via 13 and the intermediate machine language to be stored in the storage unit 303 generated by the command decoding unit 302 and the command decoding unit 502 are mixedly stored in the main storage device 600. The configuration of the storage / conversion unit 201 is shown. An instruction code having two instruction systems is stored in the main memory, and one of them is converted into an intermediate machine language by an instruction decoding section 302 via an instruction word storage section 301 and is selected by a multiplexer 603 via a bus 3021. The other is stored in the storage unit 303, and the other is the instruction word storage unit 60.
1, selected by the multiplexer 603 via the bus 6011 and stored in the storage unit 303. Multiplexer 60
3 is the first based on the contents of the flip-flop 604.
One of the contents of the bus 3021 serving as the second bus and the contents of the bus 6011 serving as the second bus is selected. Further, the instruction word stored in the main storage device 600 includes the multiplexer 6
An instruction that can switch 03 with each other is defined,
If the command is executed, the flip
The flop 604 can be controlled. On the other hand, as shown in FIG. 7, the level of the signal input to the terminal 605 is controlled by the control circuit 6
The flip-flop 604 may be controlled by detecting at 06.

The multiplexer 603 and the storage unit 303 have a structure capable of controlling the content of the instruction word storage unit 601 in units of bytes (8 bits). For an application example that does not require the instruction word storage unit 601, the bit width of the bus 213 is set. The structure allows input to the multiplexer 603.

FIG. 8 is an instruction word storage / conversion unit 2 in FIG.
It is the block diagram which subdivided the function of 01. The features of each block are shown below.

(1) Command word storage unit 301 This is a buffer memory for temporarily storing command words read from the main storage device via the bus 213. The instruction word is prefetched to enable high-speed pipeline processing.

(2) Code collating means 802 The arrangement of the operation code and the operand code differs depending on the instruction word. Therefore, the command word storage unit 301
The instruction word read out to the bus 3011 is collated with the code pattern defined and placed in the code collating means 802 to detect the coincidence.

(3) Code rearrangement information storage means 803 Defines and stores code rearrangement information for converting an instruction word into an intermediate machine language having an orthogonal instruction format. The defined rearrangement information is code collating means 802.
Is read out according to the signal 8021 from the device and sent to the bus 8031.

(4) Rearrangement means 804 In order to convert the instruction code input via the bus 3011 into an intermediate machine language having an orthogonal instruction format, the instruction code is rearranged according to the contents of the bus 8031. In the converted intermediate machine language, an operation code that specifies an operation to be executed and an operand specifier that identifies a memory location containing an operand are arranged in independent bit positions. Some instructions, except those that require no operands, include at least one operand specifier.

FIG. 9 shows an embodiment of the instruction word storage / conversion unit shown in FIG. 8, which is a first-in first-out type memory 901 serving as a memory section.
(Hereinafter, abbreviated as “FIFO”) and a control circuit 911 which is a control unit of the FIFO 901, and a command word storage unit 301 having a programmable logic array (Progra).
mmable Logic Array (hereinafter abbreviated as PLA) as a main component, a code collating unit 802 and a code rearrangement information storing unit 803, and, for example, Metal-Oxide-Semiconductor
The rearrangement information means 804 is composed mainly of a switch array using transistors (hereinafter abbreviated as MOS). Regarding the signals from a to J in FIG. 9, their timings are arranged in parallel with the basic clocks φ ₁ and φ ₂ .
It is shown in FIG.

First, the instruction read from the main memory is latched in the data buffer b via the bus a at the timing of the basic clock φ ₁ . The latched data is the basic clock φ
It is transferred to the FIFO 901 via the bus 213 at the timing of ₂ . At this time, the control circuit 911 controls the writing of data from the bus 213 to the FIFO via the signal line 9110. At the same time, an instruction to be executed is read from the FIFO 901 to the bus c and is transferred to the FIFO buffer 921.
Latched on. The code collating means 802 and the code rearrangement information storing means 803 are all composed of dynamic PLA (902, 903) which is composed of only NMOS transistors except for the precharge circuit and the driver. Therefore, input latch 912 and output latches 913, 9
14 is added. The timing from the input of the signal d to the latch 912 to the determination of the output h of the latch 913 and the output i of the latch 914 is as shown in FIG. The signal h is the instruction code before rearrangement, and the signal i
Is rearrangement information. The rearrangement unit 804 rearranges the contents of the signal h according to the signal i to obtain the signal j.

FIG. 11 is a detailed diagram of the instruction word storage unit 301 of FIG.

The FIFO 901 is a 1-port random access memory [(Randam Access Memory) (hereinafter abbreviated as RAM)].
It is composed of. Data line 1100 is the basic clock φ
_It is charged by the precharge circuit in the period of ₂ ,
Data is accessed during the period of the basic clock φ ₂ . The sense amplifier is added to amplify the accessed data. Control circuit 911
Is a write pointer (indicated by WP in FIG. 11) that specifies a write position when writing an instruction word to the FIFO 901 from the bus 213, and a read pointer (first position that specifies a read position when reading the instruction word written in the FIFO 901). (Indicated by RP in FIG. 11), and an incrementer that increases the value of each pointer.

FIG. 12 is a detailed logic circuit diagram of the control circuit 911 shown in FIG. 11. When the FIFO 901 has 8 words (1 word corresponds to the bit length of the bus 213), that is, both the write pointer and the read pointer are An example in the case of 3 bits is shown. The bus 9111 is a bus for reading and transferring the contents of the write pointer and the read pointer. Both pointers can clear the internal state by the signal. The signal ▲ indicates F when clearing the FIFO 901 when the processor 20 is reset or when a branch instruction is executed and a program is branched.
It is a signal that becomes active when the instruction word prefetched to the IFO 901 becomes invalid. Further, the signal 1200 is a signal indicating that there is no memory space in which the instruction word can be read from the main storage device to the FIFO 901, that is, the FIFO 901 is logically free and is filled with the instruction word read in advance. Further, the signal 1201 is sent from the main storage device to F
There are 8 words of memory space which can read the instruction word in IFO901, that is, the pre-read instruction word is FI.
This is a signal indicating that there is no one in FO901. A signal 1202 is a write pointer increment signal, a signal 1203 is a read pointer increment signal, a signal 1204 is a signal for outputting the contents of the write pointer to the bus 9111, and a signal 1205 is a signal for outputting the contents of the read pointer to the bus 9111.

FIG. 13 shows another embodiment of the instruction word storage unit 301 of FIG. 9, which is a configuration example when the FIFO 901 is controlled by the PLA. At the same time, control for fetching an instruction word from the main storage device to the FIFO via a 32-bit bus and control for transferring the contents of the FIFO to the instruction decoding unit with a 16-bit length are performed. The PLA controlling the input / output of data to / from the FIFO satisfies the FIFO control state diagram shown in FIG. The state of PLA1300 is 14th
The state transits from ₁₀ states S ₁ to S ₁₀ shown in the figure, but in all states, when the FIFO / Reset signal is input, the state becomes S ₁ . States S ₁ and S ₆ are FI
The FO 1301 shows an empty state (Enpty: indicated by E in FIG. 14), that is, a state in which no instruction word has been fetched. Further, in the states S ₃ , S ₅ , S ₈ and S _10, the area for storing the newly fetched instruction word is the FIFO 1301.
It is a state (Full: indicated by F in FIG. 14) indicating that it does not exist inside.

On the other hand, each state (S _{1 to} S ₁₀ ) has a state storage unit 130.
2 is stored in the status storage unit 1302, and when the new status is output from the PLA 1300, the status is set in the status storage unit 1302 by the signal 13002.

FIG. 15 shows another embodiment of the FIFO 901 shown in FIG. 11, in which the bit length for inputting data to the FIFO 901 (the number of bits of the bus 213) and the bit length for reading out the data stored in the FIFO 901 are 2: 1. 2 shows an example of the configuration of the FIFO 901 when read and write control is performed. There are two word lines (1500) that control reading and writing of the memory cell 1110.
1, 15002).

FIG. 16 is a detailed logic circuit diagram of the control circuit 1510 for controlling the input / output of the FIFO 1500 shown in FIG. First
Compared to FIG. 2, the feature is that there are two read pointers (RP _H , _R PL), and the data in the FIFO is ½ word long by these two read pointers _{R P H} , _{R P L.} Can also be handled as a 1-word length.

FIG. 17 shows an example of the configuration of a control circuit for always defining the head of data from the upper bits when the data in the FIFO 1500 is handled in a 1/2 word length. First, the flip-flop 1700 is set to the signal 170 at the same time as the reset of the FIFO 1500 and the control circuit 1510.
Reset by 01 (state 0). After reset, flip-flop 1700 selects latch 1702. When the data in the FIFO 1500 is handled with a length of 1/2 word, the flip-flop 1700 is set by the signal 17002 (state 1). At this time, the output signal of the flip-flop selects the latch 1701. Further, when the data in the FIFO 1500 is handled in a half word length, the flip-flop 1700 is reset by the signal 17002 (state 0). By repeating the above operation, the beginning of the data can be known.

FIG. 18 is a detailed diagram of a part of the flip-flop shown in FIG. 17, and FIG. 19 is its timing chart.

FIG. 20 shows the code collating means 8 shown in FIGS. 8 and 9.
02, code rearrangement information storage means 803, rearrangement means 8
This shows an example of the configuration of 04. Each signal line d, e, f, g, h, i and j is the same as the corresponding signal shown in FIG. 9, and its timing chart is
It is as shown in FIG. Code matching means 802 is AND
Type dynamic PLA, and the code rearrangement information storage unit 803 is configured by an OR type dynamic PLA. The rearrangement means 804 is an N channel type MOS.
A transistor is used as shown in the figure. The most important feature of this configuration is the microprogram storage /
Signals to be input to the control unit 202 and the decoder unit 203, that is, information j to be stored in the storage unit 303
When generating, the command word (signal line d) is not decoded to generate a new binary code (corresponding to information j) which is completely different from the command word, but the binary code expressing the command word The information j is generated by using some or rearranging all of them. Further, in order to rearrange the binary code of the command word, even if the code of the command word is completely different, the rearrangement information is defined so that the command words of the procedure in which the rearrangement format is completely the same are the same array. It is a point. According to this embodiment,
It is possible to realize the function of an instruction decoder that has conventionally generated a microprogram address that is an input of a microprogram storage / control unit from an instruction word, and in addition, with about 1/5 to 1/10 the hardware of the decoder. The same function can be realized.

FIG. 21 shows another embodiment of the rearrangement means 804 of FIG. 20. The difference from FIG. 20 is that information j is output according to the output of the OR array (code rearrangement information storage means 803) of PLA.
The point is that can be specified arbitrarily. In the embodiment of FIG. 20, some or all of the instruction codes are rearranged to obtain the information j.
In this embodiment, a code independent of the instruction code can be used as the information j. That is, the information j having an arbitrary code pattern regardless of the binary code expressing the command word can be obtained only by changing the contents of the code rearrangement information storage unit 803.
Can be obtained.

FIG. 22 shows an example in which the contents of the code collating means 802 shown in FIG. 8 are constituted by memory cells which can be read and written so that they can be dynamically converted.

Information for collating the instruction code is sequentially defined word by word in the memory cell 2210 via the bus 22001. After defining all the bits of the memory cell 2210, the command word to be collated is input to the data line 22101 via the bus d. The memory cell 2210 compares the defined content with the content of the data line 22101 and drives the signal line 22102 to the low level when they do not match. When all the bits in one word match, the signal line 22102 goes High.
Maintain the h level. Matched signal line 22102
At least one of the signal lines drives the rearranged code rearrangement information storage unit 803.

FIG. 23 is a detailed view of an example of the memory cell 2210 of FIG.

When data is written in the memory cell 2210, it is controlled by the signal line W. Further, although the polarities of the data lines D and are inverted, they are driven to the High level during the precharge cycle. At this time, since the signal line C is driven to the Low level, the precharge operation is preferable for the code rearrangement information storage unit 803.

FIG. 24 shows a microprogram storage / control unit 20.
It is a figure which shows one Example of a structure of 2.

A part of the microprogram address to be set in the microprogram address register 2403 is selected by the selector 2
Signal 2402a selected by 402 and signal 2406 which is part of the output of microinstruction register 2406
e is combined and stored in the microprogram address register 2403. The output of the micro program address register 2403 is sent to the address decoder 2404, while the micro program incrementer 240
8 is incremented by 1 and the signal is output as a signal 2408a.
Sent to 2. The address decoder 2404 decodes the micro program address and sends the result to the micro instruction storage unit 2405. Micro instruction storage unit 24
At 05, the designated micro instruction is read out and stored in the micro instruction register 2406. The output of the micro instruction register 2406 is roughly classified into three, and a signal 2406a
Is a signal for controlling the decoder unit 203 and the arithmetic unit 204, a signal 2406b is a signal for designating a branch destination address when a branch occurs in the microprogram, and a signal 2406c is a signal for controlling the next address of the microprogram. Is. The control circuit 2407 controls the signal 2406c according to the signal 2406c.
407a is a control circuit for generating a signal 2407b for controlling the stack 2409 for saving the microprogram address.

FIG. 25A shows the microprogram address register 2403 and the address decoder 240 shown in FIG.
4, an example of the microinstruction storage unit 2405 and the microinstruction register 2406 is shown.

One bit of the microprogram address register 2403 has a configuration shown by a flip-flop 2503 as shown in FIG. 25 (b), for example. The address decoder 2404 is an AND type dynamic PLA, and the microinstruction storage unit is an OR type dynamic PLA. The micro instruction register 2406 is composed of a dynamic latch.

FIG. 26 shows the timing of each signal alongside the basic clocks φ ₁ and φ ₂ . As is apparent from FIG. 26, the output 2403 of the microprogram address register 2403
It takes one clock cycle until the output of the micro instruction register 2406 is obtained after a is determined.

FIG. 27 shows the timing of each signal when the microprogram storage / control unit 202 is stopped without stopping the basic clocks φ ₁ and φ ₂ . The signal 24A is the microprogram storage / control unit 20.
2 is a signal that gives a stop to the microprogram address register 240.
3 is stopped and the micro instruction register 240 is stopped.
The outputs of 6 are all at low level. Unique value of the micro instruction register at this time (all must be Low level)
Is a state in which the controlled system apparently does nothing (so-called
By setting the No OPeration state), the microprogram storage / control unit 202 can be apparently stopped. The example of FIG. 27 shows the microinstruction 2 (μIR2 in the figure).
2) and the microinstruction 3 (expressed by μIR3 in the figure) for one clock cycle (indicated as Nop in the figure).

FIG. 28 shows the configuration of the operation control decoder 2030 in the decoder unit 203. The decoder control latch 2800 and the register control first decoder 28 are shown in FIG.
10, a register control second decoder 2820, an arithmetic circuit control decoder 2840, and delay circuits 2830 and 2850. The register control first decoder 2810 is a part that specifies a source register in which data to be calculated is stored, and the register control second decoder 2820 is a part that specifies a destination register in which a calculation result is stored. The decoder 2840 specifies the type of operation (addition, subtraction, logical sum, logical product, exclusive logical sum). Since one clock cycle is required from the reading of the source register to be operated and the operation to the determination of the result, the delay circuit 2830 delays the signal 2801 by one clock cycle. Arithmetic circuit control decoder 28
Since the output signals 2841 and 2842 of 40 use different timings, the delay circuit 2850 delays the signal 2842.

FIG. 29 shows the decoder control latch 28 of FIG.
00, the first register control decoder 2810, the second register control decoder 2820, and the delay circuit 2830.

The most characteristic feature of this embodiment is that the register control first decoder 2810 and the register control second decoder are constituted by AND type dynamic PLA, and the output line 28 of the PLA is formed.
12 is precharged by a P-channel type MOS transistor, and the peculiar level (High level in this embodiment) of the signal 2812 output during the precharge period is set to a non-selected state with respect to the input / output of the register, and the precharge period After completion of the above, only the signal line 2812 for which the logic of PLA is established is charged, and the input / output signal line 2813 of the register is brought into the selected state of the register.

FIG. 30 shows the timing of each signal of the register control first decoder 2810 alongside the basic clock. It takes one clock cycle from the determination of the output 2801 of the decoder control latch 2800 to the determination of the register read control signal 2811 and the reading of the contents of the register. That is, according to this embodiment, the amount of hardware can be reduced to about 1/3 that of the static PLA, and the outflow of charges from the signal line 2812 is reduced only in the selected signal line. It becomes possible to operate at the same register access timing as the static decoder.

When the logical sum of the output lines of the PLA is required, the logical sum can be obtained by forming a wired OR configuration in which the output lines are directly connected.

FIG. 31 shows an example of the configuration of the arithmetic unit 204, which is a temporary register 310 for temporarily storing data.
0, status register 31 that stores the status of the operation result
10, an arithmetic circuit 3120, a source latch 3130 for temporarily storing data to be operated, a shift circuit 3140 for shifting the operation result to the left 1 bit or the right 1 bit, a destination latch 3150 for temporarily storing the operation result, and a read from the bus 213 And a write data register 3170 for temporarily storing the data to be output to the bus 213.

First, one of the data to be calculated is sent to the source latch 3130 via the bus 31A. At this time, the source latch 31
The contents of 30 and the contents of the read data register 3160 are input to the arithmetic circuit, and the arithmetic designated by the signal line 2823 is performed. The operation result is the destination latch 315.
It is temporarily stored at 0 and written to the register designated by the signal 2813 via the bus 31B. On the other hand, the signal indicating the sign of the result according to the operation result, the signal indicating that the result was zero, the signal indicating the carry (borrow) of the operation result, and the signal indicating the overflow at the time of operation are all signal line 3
It is input to the status control circuit 3180 via 1C and the state of the signal designated by the signal 2803 which is a part of the microinstruction is stored in the status register 3110.

32, 33 and 34 show an example of a detailed circuit diagram of each component of the arithmetic unit 204 shown in FIG.

The buses 31A and 31B are precharged while the basic clock φ ₁ is at the high level, and the basic clock φ ₂ is Hi.
Data is transferred during the gh level period.

(1) 1-bit Configuration of Temporary Register 3100 The 1-bit configuration of the temporary register 3100 is, in terms of the least significant bit, a write gate 3101-0 and a drive gate 3103-connected to the bus 31B-0.
0, a feedback gate 3102-0, and a read gate 3104-0 connected to the bus 31A-0. The write operation of the temporary register sets the control signal 3200a to H level.
By setting to high, the writing gate 31B-0
Is passed through the write gate 3101-0. On the other hand, in the read operation, the control signal 3200b is set to H level.
drive gate 3103-
The output of 0 is applied to the read bus 31A-0 via the read gate 3104-0.

(2) Status Control Circuit 3180 and Status Register 3110 The status control circuit 3180 is a PLA that receives the microinstruction 2803 and the status information 31C of the operation result, and outputs the set signal 3281 to be written to the status register and the data 3283 to be written. The status register 3110 has a structure in which an input gate 3110-0 is added, as compared with the least significant bit of the temporary register 3100, in terms of the least significant bit. The point to be noted here is that data 32 is passed through the gate 3110-0.
The operation of writing 82 is the bus 31 in the arithmetic unit 204.
It is being done in the precharge period of A and 31B.

(3) Source latch 3130 A dynamic latch that temporarily stores operation data,
Data can be inverted and input according to the control signal 2813.

(4) Operation circuit 3120 According to the three control lines 3321, addition, logical sum, logical product, and exclusive logical sum can be obtained.

(5) Shift circuit 3140 The left and right 1 bit can be shifted according to the signal line 3341. By setting the signal line 3341R to High, 1-bit right shift is performed, and by setting the signal line 3341L to High, 1-bit left shift is performed.

(6) Destination latch 3150 This is a dynamic latch that temporarily stores the output of the shift circuit 3140. It is the only source that can output data to the bus 31B.

(7) Read Data Register 3160 and Write Data Register 3170 The read data register 3160 temporarily stores the content of the bus 213, and the content is either one of the inputs of the arithmetic circuit 3120 or is transferred to the bus 31A. On the other hand, the write data register 3170 temporarily stores the data to be output to the bus 213, and the content thereof is input from the bus 31B via the operation result.

In FIG. 34, the bus 213 has 16 bits, the read data register 3160 and the write data register 3170.
Is a 32-bit configuration, the bus 213
Signals 236a, 236b, 236 for controlling input / output to / from
c and 236d are the lower 1 of the input / output of the two registers.
6 bits and upper 16 bits are controlled independently.

FIG. 35 shows an embodiment of the processor 20 including the main memory 3500 capable of at least read operation.

When the processor 20 is reset, the level detection / storage circuit 3531 detects the level of the terminal 3530 and stores the content.

The operation example will be described separately for the following two cases.

(1) Operation when the output 3532 of the level detection / storage circuit 3531 is at the Low level The content of the memory address register 1 (indicated by MAR1 in FIG. 35) is transferred to the bus 213, and the terminal 3521 is transferred via the buffer 3520. Transfer to. The multiplexer 2 (displayed as MPX2 in the figure) 3530 selects the content of the bus 213 and applies it to the main storage device 3500. When the internal contents of the bus 212 indicate the address of the main storage device outside the processor 20, the contents of the bus 213 input from the terminal 3511 are selected by the buffer 3510. On the other hand, when the content of the bus 213 indicates the address of the main storage device in the computer, the content of the bus 3501 is selected by the buffer 3510. The buffer 3510 is controlled by the output 3561 of the decoder 3560 which decodes whether or not the address, which is the content of the bus 212, indicates the main memory device 3500 in the processor 20. Output 35 of buffer 3510
12 is a multiplexer 1 (indicated by MPX1 in the figure) 35
It is selected at 40 and transferred to the command word storage unit 301.

(I) Instruction fetch The instruction fetch is performed in the memory address register 1 (MAR
The contents of the instruction address register (IAR) are set in 1) and the main memory is read.

(Ii) Data read and write Data read and write are performed by the data address register (D
AR) contents are stored in memory address register 1 (MAR1)
, And the main memory is read and written. The arithmetic unit 204 has already calculated the effective address in the data address register (DAR) at this time, and the content thereof is set in the DAR.

(2) Operation when the output 3532 of the level detection / storage circuit 3531 is at the high level (i) Instruction fetch The contents of the instruction address register (IAR) are set in the memory address register 2 (MAR2), and the bus 3502 is connected. The content of the bus 3502 is selected by the multiplexer 2 (MPX2) which is transferred to the multiplexer 2 (MPX2) 3550 via the multiplexer 2 (MPX2) and applied to the main storage device 3500. On the other hand, the output of the main storage device 3500 is selected by the multiplexer 1 (MPX1) via the bus 3501 and the instruction word storage unit 301
Transferred to.

(Ii) Data Read and Write The effective address in the data address register (DAR) already calculated by the arithmetic unit 204 is transferred to the memory address register 1 (MAX1) and transferred to the buffer 3520 via the bus 212. The contents of the buffer 3520 are applied to the main memory outside the processor 20 via the terminal 3521. On the other hand, data to be read or written, via the terminal 3511 and the bus 213, the arithmetic unit 204 in the processor 20 and the main storage device outside the processor 20, or the processor 20 connected to the bus 213.
It is sent and received to and from the main storage device inside.

That is, when the output 3522 of the level detection / storage circuit 3531 is at the high level, the instruction fetch is performed from the main storage device 3500 included in the processor 20, and the reading and writing of data is performed by the main storage device other than the main storage device 3500. It is characterized in that it operates with a device, and fetches instructions and reads and writes data at the same time. Therefore, according to the present embodiment, the instruction fetch and the data read / write can be performed at the same time, so that the instruction word processing time is shortened.

FIG. 36 shows an embodiment of the processor 20 in which the memory access cycle (instruction fetch cycle, data read cycle, data write cycle) is variable.

Register 36 that can be read and written by instructions
The access cycle of the memory is made variable according to the contents of 00. FIG. 37 shows an example in which the memory access cycle is changed according to the value in the register 3600. Third
When the register value is 0 as shown in FIG. 7A, the fastest memory access is performed. Therefore, by configuring the microprogram storage / control unit 202 adapted to this case, when the register value is 1, the memory access control circuit stops the microprogram storage / control unit 202 for the signal 24A for one clock cycle. Memory access can realize 3 clocks.

That is, according to this embodiment, the access cycle of the main memory used in combination with the processor 20 can be changed by designating the value of the register by the instruction, and the main memory used changes its access cycle. Even if the value changes, it can be adapted without adding an extra control circuit outside the processor 20.

〔The invention's effect〕

According to the present invention, even if the instruction format of an instruction word to be processed is changed, it is possible to deal with it without changing or adding all the hardware in the processor except the instruction word storage / conversion unit, and the hardware for decoding the instruction word can be handled. The wear scale can be realized by 1/5 to 1/10 of the conventional instruction decoder system.

Further, according to another feature of the present invention, it is possible to process an instruction word having at least two types of instruction formats.

[Brief description of drawings]

FIG. 1 is a block diagram of a processor showing an embodiment of the present invention,
FIG. 2 is a block diagram of a single chip microcomputer showing an embodiment of the present invention, FIGS. 3 to 23 are block diagrams of an instruction word storing / converting unit showing an embodiment of the present invention, and FIGS. 24 to 27. The figure shows an example of the configuration of the microprogram storage / control unit, FIGS. 28 to 30 show an example of the configuration of the decoder unit, and FIGS. 31 to 34 show an example of the configuration of the arithmetic unit. Figure, Figures 35 to 3
FIG. 7 is an explanatory diagram relating to memory access. 20 ... Processor, 201 ... Command word storage / conversion unit, 202 ... Microprogram storage / conversion unit, 203 ... Decoder unit, 204 ... Arithmetic unit, 205 ... Bus interface unit.

Claims (10)

[Claims] 1. At least one of the command words including operation information designating an operation to be executed,
An instruction word including at least one operand designation information for identifying the position of the main storage device including the operand, the instruction word being successively input in a data processing device which processes the operand in response to the instruction word. And an instruction word storage unit that is connected to the instruction word storage unit and detects the positions of the operation information and operand designation information included in the instruction word to specify the operation information and the operand designation. The instruction decoding means capable of independently extracting information, and a storage portion connected to the instruction word storage means and having a predetermined bit position for storing operation information and operand designation information are provided. The operation information and the operand designation information included in the word are extracted, and the defined bit position of the storage unit is extracted. A data processing device, characterized in that the data is re-arranged in a storage unit and stored, and processing is performed according to the contents of the storage unit. 2. The data processing device according to claim 1, wherein the instruction word is an instruction word having at least two instruction formats having different binary codes expressing the instruction even though the instruction functions are the same. When the operand is processed in response to an instruction word expressed and having the at least two types of instruction formats, the instruction decoding means detects the position of the operation information and the operand designation information included in the instruction word. The operation information and the operand designation information are independently extracted, and the plurality of instruction decoding means corresponding to the plurality of instruction formats of the instruction word in the main memory are provided, and the plurality of instruction decoding means are further provided. A multiplexer for selecting any one of the outputs and a control unit for controlling the multiplexer. A data processing device, characterized in that processing is performed corresponding to an instruction word having at least two types of instruction formats. 3. The data processing device according to claim 1, wherein the instruction word is an instruction word having at least two instruction formats having different binary codes expressing the instruction even though the function of the instruction is the same. In the case of processing the operand in response to the instruction word expressed and having the at least two types of instruction formats, the instruction word storage means normally retrieves the instruction words successively input from the main storage device. And a plurality of instruction word storage means corresponding to a plurality of instruction formats of instruction words in the main storage device, and further, operation information and operand designation included in the instruction word read from the main storage device. A first bus for transferring the information extracted and rearranged for storing the information in a predetermined bit position of the storage unit; a second bus connecting the storage unit and the main storage device; A multiplexer that can select either the first bus or the second bus and a control unit that can control the multiplexer are provided, and at least two types of instruction formats read from the main storage device are provided. A data processing device characterized by performing processing corresponding to a command word that it has. 4. The data processing device according to claim 2 or 3, wherein the control means for controlling the multiplexer executes an instruction in the main memory or an instruction given from another, A data processing device capable of controlling the control means. 5. The data processing device according to claim 1, wherein the instruction decoding means collates predetermined information with an instruction code and detects the coincidence, and the code. A code rearrangement information storage means capable of defining arrangement information for changing the arrangement of all or part of the instruction code in response to the result of the collating means, and an instruction according to the arrangement information connected to the code rearrangement information storage means And a rearrangement means for rearranging codes, wherein a result of the rearrangement means corresponding to the instruction code is used as an address of a microprogram memory. 6. A data processing apparatus according to claim 5, wherein at least one of the code collating means and the code rearrangement information storing means is composed of a programmable storage element (Programmable Logic Array). A data processing device that features things. 7. The data processing device according to claim 5, wherein the code collating means is a storage element (Random Access Memory) capable of being read and written at any time, and stores the content of the storage element and the content of the data line. A data processing device comprising a memory cell capable of detecting a match. 8. The data processing device according to claim 1, wherein the instruction word storage unit includes a memory unit that stores the instruction word, and a control unit that controls reading and writing of data with respect to the memory unit. And a data processing device characterized by being capable of reading out a data length that is half the data length handled in one write operation. 9. The data processing device according to claim 8, wherein the control unit for controlling the memory unit is composed of a programmable storage element (Programmable Logic Array). . 10. A data processor according to claim 1, 2, 3, 5 or 8, wherein a main memory for storing said instruction and operand and said data processor are one-chip semiconductor substrates. A data processing device configured as described above.