JPH05204635A - Register control system - Google Patents

Abstract

PURPOSE:To speed up processing applied to different architecture parts by making it possible to execute the architecture parts having respectively different register sizes by the same hardware, allowing both architecture parts to share mutual register data, and eliminating the necessity of the saving/restoring operation of registers at the time of switching respective architecture parts in respect to a register control system for controlling registers to be used by respective architecture parts. CONSTITUTION:This register control system is provided with a register address conversion means 2 for converting the register numbers of instructions applied from respective architecture parts having respectively different register width into a common register number, and a general register 3 having the same width as larger width out of the different register width values of respective architecture parts and constituted so that the means 2 converts the address of an instruction outputted from the architecture part whose execution is specified into a common register number and the register 3 is accessed by the converted register number.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register control system for controlling registers used by different architectures.

[0002]

2. Description of the Related Art Conventionally, two different architectures have been
In the case of support by one processor, it is conceivable that the hardware itself is separately provided for each architecture and the architecture of the general-purpose register is allocated for each architecture. Alternatively, the hardware itself is shared, and when the architecture is switched, the contents of all general-purpose registers are saved,
It is possible to restore it when returning to the original architecture.

[0003]

When the different architectures described above are to be realized on one LSI, providing a general-purpose register for each of the former architectures would increase the amount of hardware, resulting in an incompatibility. There is a problem that there is no situation.

When the latter one general-purpose register is shared by two architectures to be realized on one LSI, it is necessary to save / restore all the contents of the general-purpose register every time the architecture is switched. Therefore, there is a problem that performance is deteriorated due to a loss of execution time.

The present invention solves these problems.
A register address conversion unit for commonizing register numbers of different architectures is provided so that architectures having different register sizes can be executed on the same hardware, and register data is shared between architectures to register registers when switching architectures. The purpose is to eliminate the save / restore of, and to speed up the process across architectures.

[0006]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, the register address conversion means 2 converts the register number of an instruction of an architecture having a different register width into a common register number.

The general-purpose register 3 is a register having a large width among the register widths of different architectures.
The writing unit 4 writes data in the general-purpose register 3.

The reading means 5 reads data from the general-purpose register 3.

[0009]

According to the present invention, as shown in FIG. 1, the register address conversion means 2 converts the address of the instruction of the architecture instructed to be executed into a common register number, and the general register 3 is converted by the converted register number. I try to access it.

Further, the register address conversion means 2 converts the address of the architecture-instructed instruction having a small register width into a common register number that has been packed, and the general register 3 is converted by the converted register number.
The writing means 4 writes the part of the data read by the reading means 5 and the data to be written into the general-purpose register 3 together.

Further, the register address converting means 2 converts the address of the instruction of the architecture instructed to be read out having a small register width into a packed common register number,
The data read from the general-purpose register 3 by the reading means 5 is aligned with the data of the original register width and output based on the converted register number.

Further, among the converted common register numbers, a register having a register number shared by both architectures is used as a data transfer register between the two in order to increase the speed.

Therefore, by providing the register address conversion means 2 for making register numbers of different architectures common, architectures having different register sizes can be executed on the same hardware.
In addition, by sharing the data of the registers shared by the architectures and eliminating the save / restore of the registers when switching the architectures, it is possible to speed up the processing across the architectures.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be sequentially described in detail with reference to FIGS.

FIG. 1 is a block diagram showing the principle of the present invention. Figure 1
(A) shows a configuration diagram. In FIG. 1A, the buffer 1 holds an instruction. Here, the buffer 1 is provided for each of the different architectures A and B. Of the instructions held in the buffer 1, the REG portion that uses the general-purpose register 3 is taken out, input to the register address conversion means 2, and converted into a common register number.

The register address conversion means 2 converts register numbers used by instructions of different architectures into a common register number. General-purpose register 3
Is a general-purpose register that can be accessed at high speed and is used when executing an instruction. Here, it has a port for independently inputting a read address (register number when reading) and a write address (register number when writing).

The writing means 4 writes the write data to the general-purpose register 3, or writes a part of the write data together with a part of the merge read data read from the general-purpose register 3 to the general-purpose register 3. It is something to write in.

The reading means 5 reads data from the general-purpose register 3. FIG. 1B shows address mapping of the general-purpose register 3. Since the GR (general-purpose register 3) of architecture A has a larger size (register size (data length) and register number) than the GR of architecture B, the size of the general-purpose register 3 is the entire size.

GR (general purpose register) of architecture B
Since the size (register size (data length) and register number) is smaller than GR of architecture A, a part of the general-purpose register 3 is used. On this occasion,
The dotted line indicates that the register size of architecture B is 1
If the architecture A has a register size of 6 bits and the register size of architecture A is 32 bits, which is exactly half, the architecture B
2 shows that the two registers are allocated to one register of architecture A (described later with reference to FIG. 3).

As described above, the general-purpose register 3 for the architecture A having the large register size is provided and the architecture B having the small register size is provided as shown in FIG. For efficient allocation of a part of the general-purpose register 3 as shown in FIG. 1B, the register address conversion means 2 converts the common register number (register address) to access the general-purpose register 3. A specific description will be given below with reference to FIG. 3 based on the configuration of FIG.

FIG. 2 shows a block diagram of an embodiment of the present invention.
Here, as shown in (a) of FIG. 3, architecture A register length is 32 bits Register number is 00 to 31 (4 bits length) Architecture B register length is 16 bits (half of architecture A) Register number is 00 to 15 (half of architecture A).

In FIG. 2, a buffer 1 is a buffer that holds the instructions of architectures A and B. The register address conversion unit 2 converts the register numbers of the architectures A and B into the register numbers of the common general-purpose register 3, and is composed of an address conversion unit 21, a multiplexer 22, and the like.

The address conversion unit 21 has an architecture B
The upper 2 bits are generated in the 4 bits. The upper 2 bits are for selecting any of the four blocks 00, 01, 10 and 11 of FIG.

The multiplexer 22 selects any one of the 6 bits of the architectures A and B. The general-purpose register 3 has a read port and a write port, and both can read / write independently.

The write buffer 6 is a buffer that holds data to be written. The multiplexer 7 selects either the lower data from the write buffer 6 or the lower data read from the general-purpose register 3.

The multiplexer 8 has upper data from the write buffer 6, lower data from the write buffer 6,
Alternatively, one of the higher-order data read from the general-purpose register 3 is selected.

The multiplexer 9 is for selecting and aligning either upper data or lower data read from the general-purpose register 3. The multiplexer 10 selects either the high-order data read from the general-purpose register 3 or the high-order 0 data.

The read buffer 11 is a buffer that holds the data read from the general-purpose register 3. Figure 3
The operation explanatory drawing of this invention is shown.

First, the outline of FIG. 3 will be described. FIG. 3A shows GR of architecture A and architecture B.
Shows the register length and register address of GR.

Here, the GRs (general purpose registers) of the architecture A are 32 bits (register length (data length)) of 00 to 31 (5 bits length) and 32 register addresses (register number) of 00 to 31. .. On the other hand, the GR (general-purpose register) of architecture B has 16 bits with a register length (data length) of 00 to 15 and 16 register addresses of 00 to 15. Therefore, as the general-purpose register 3, the register length of the architecture A having a large size is 32 bits and the register address is 32.

FIG. 3B shows address mapping. The arche A (arche A in FIG. 2) adds one bit of 0 to the lower 5 bits of the register addresses 00000 to 11111 in FIG. Bit. The upper 5 bits are a register address for accessing the general-purpose register 3.

Arche B (Arche B in FIG. 2) has register address 00 in FIG. 3 (a) as indicated by the arrow.
For the 4 bits from 00 to 1111, the higher bits 00, 0
The address of any one of blocks 1, 10, and 11 is generated and added by the address conversion unit 21 in FIG. 2 to make a total of 6 bits. When the lower 1 bit of these is an even number, the multiplexer 7 selects the lower data from the write buffer 6 and writes it to the lower of the general-purpose register. On the other hand, when the lower 1 bit is an odd number, the multiplexer 8 selects the lower data from the write buffer 6 and writes it in the upper of the general-purpose register. As a result, as shown in the general-purpose register 3 described on the right side of FIG. 3B, the lower register of the same register number writes the even-numbered data of the lower-order 1 bit, and the upper register writes the data of the lower-order 1 bit of the odd number. So to speak 16
It becomes possible to write two bits of register length data into the general register 3 having a register length of 32 bits.

FIG. 3 (c) shows the mapping of Arche B. This is 00, 01, 1 when the upper 2 bits of the arche B described above in FIG. 3B are generated and added.
Corresponding to 0 and 11, it is determined which one of the quarter blocks shown in the figure should be selected. For example, when 00 is selected as the high-order bit, the low-order 1 bit of 2 bits is written to each of the 8 register numbers from 00 to 07 and the odd-numbered and even-numbered data is written to fill 16 data in total. It will be written.

Next, the operation of the configuration shown in FIG. 2 will be described in detail with reference to FIG. (1) Writing architecture A data. (1-1) The lower 1 bit of 0 is added to 5 bits of the register address in the instruction held in the buffer 1 of FIG. 2 to make a total of 6 bits.

(1-2) The 6 bits generated in (1-1) are selected by the multiplexer 22, the multiplexers 8 and 7 are selected by the architecture A, and the upper and lower data are written from the write buffer 6. Input to the general-purpose register 3 and write. At this time, the upper 5 bits are input from the write port of the general-purpose register 3 to select an arbitrary register address.

As described above, in architecture A, the data (32-bit length) in the write buffer 6 is written in the general-purpose register 3. (2) Reading data of architecture A.

(2-1) The lower 1 bit of 0 is added to 5 bits of the register address in the instruction held in the buffer 1 of FIG. 2 to make a total of 6 bits. (2-2) The multiplexer 22 selects the 6 bits generated in (2-1), and according to the architecture A,
The multiplexers 10 and 9 select to read data from the general-purpose register 3 and store it in the read buffer 11.

As described above, in architecture A, the data (32-bit length) is stored in the read buffer 11 from the general-purpose register 3. (3) Writing data of architecture B.

(3-1) The address conversion unit 21 generates and adds the upper 2 bits to the register address and the 4 bits in the instruction held in the buffer 1 of FIG. 2 to make a total of 6 bits.

(3-2) The 6 bits generated in (3-1) are selected by the multiplexer 22, and by the architecture B and the lower 1 bit, an even number of 0 (or an odd number of 1). Select (or) to select general register 3
The upper data read from the write buffer 6 and the lower data from the write buffer 6 are written together in the general register 3 (or the upper data from the write buffer 6 and the general register 3 are written together).
The lower-order data read from is written in the general-purpose register 3 together).

As described above, in the case of architecture B, the data (16-bit length) in the write buffer 6 is sequentially written in the lower and upper parts of the general register 3 (see the general register 3 on the right side of FIG. 3B).

(4) Reading of architecture B data. (4-1) The address conversion unit 21 generates and adds the upper 2 bits to the register address and the 4 bits in the instruction held in the buffer 1 of FIG. 2 to make a total of 6 bits.

(4-2) The 6 bits generated in (4-1) are selected by the multiplexer 22, and are selected by the multiplexer 10 and the multiplexer 9 by the architecture B and the lower 1 bit, which is an even number of 0 (or an odd number of 1). 0 "(or" 0 ") is selected, and data read from the general-purpose register 3 is stored in the read buffer 11 with 0 as the higher order.

As a result, the upper part of the read buffer 11 can always store 0, and the lower part can store data from the lower or upper part of the general register 3 and output 16-bit data.

As described above, the lower or upper data read from the general register 3 in the architecture B is sequentially stored in the read buffer 11 and aligned. In addition, by setting a block that shares data with the architecture A for the 2 bits added to the upper 4 bits of the architecture B, the architecture A and the architecture B use the same general-purpose register 3 to exchange data. Yes, you can speed it up. At this time, the general-purpose register 3 to be used independently between the two is separately used so that save / restore is eliminated.

[0046]

As described above, according to the present invention,
Since the register address conversion means 2 for commonizing register numbers of different architectures is provided and the general-purpose register 3 is shared, architectures having different register sizes can be executed on the same hardware. it can. Further, it is possible to share the data of the general-purpose register 3 shared by the architectures to eliminate the saving / restoring of the registers at the time of switching architectures, thereby speeding up the processing across the architectures.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the present invention.

[Explanation of symbols]

 1: Buffer 2: Register address conversion means 3: General-purpose register (GR) 4: Writing means 5: Reading means 6: Write buffer 7, 8, 9, 10, 22: Multiplexer 11: Read buffer 21: Address conversion unit

Front page continuation (72) Inventor Kazuyasu Nonomura 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Toru Watanabe 1015, Kamedotachu, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takumi Maruyama 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Shinya Kato 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (4)

[Claims] 1. A register control method for controlling registers used by different architectures, and register address conversion means (2) for converting a register number of an instruction of an architecture having a different register width into a common register number, and a register of a different architecture. A general-purpose register (3) having a larger width, and the register address conversion means (2) converts the address of the instruction of the architecture instructed to be executed into a common register number, and the register after the conversion A register control system characterized in that the general-purpose register (3) is accessed by a number. 2. A register address conversion means (2) for converting a register number of an instruction of an architecture having a different register width by an integral multiple in a register control system for controlling registers used by different architectures to a common register number. The register address conversion means (2) comprises a general-purpose register (3) having a large width among register widths of different architectures, and a writing means (4) for writing data read from the general-purpose register (3). The address of the architecture-designated instruction having a small register width is converted into a packed common register number, and the converted register number is used to write a part of the data read from the general-purpose register (3). The data to be written together, and the writing means (4) makes the general-purpose register (2 )
A register control method characterized by being configured to write to. 3. A register control method for controlling registers used by different architectures, and register address conversion means (2) for converting a register number of an instruction of an architecture whose register width differs by an integral multiple into a common register number. A general-purpose register (3) having a large width among register widths of different architectures and a reading means (5) for reading from the general-purpose register (3) are provided, and the register for which the register address conversion means (2) is instructed to read. The address of the instruction of the architecture having a small width is converted into the packed common register number, and the data read from the general-purpose register (3) by the reading means (5) is converted by the converted register number.
A register control method characterized by being configured to output data aligned with the original register width. 4. Among the converted common register numbers,
4. The register control method according to claim 1, wherein a register having a register number shared by both architectures is used as a data transfer register between the two so as to increase the speed. ..