JPH07134677A - Register write system - Google Patents

Abstract

PURPOSE:To reduce the number of execution cycles by employing such constitution that the number of write ports can be reduced by unifying register groups and write on the register groups can be performed even when a start address is not the one of eight byte boundary as a register write system. CONSTITUTION:This system is comprised by providing a buffer RDB which holds data read out from memory 1 in boundary unit, an alignment ALM which arranges by sampling the data in accordance with an even-numbered or odd- numbered start register number from the data read out from the memory 1 in boundary unit and the data just before read out from the buffer RDB, a register RD which stores arranged data, and the register group 2 that is a set of registers for which the data read out from the register RD is designated and which perform write from an even-numbered or odd-numbered start register number position.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register write system for writing data read in boundary units of a memory from even or odd positions in a register.

[0002]

2. Description of the Related Art Conventionally, when data is written to a register group 47 shown in FIG. 14B from a memory (main memory) 41 via a bus under the configuration of FIG. Will be described below.

In FIG. 14B, a register group 47 is provided.
Is composed of a plurality of registers each having a width of 2 bytes, and R0, R2, R4, ...
2n and R1 and R of odd-numbered registers (referred to as RO)
3, R5 ... R2n + 1.

In FIG. 14A, the memory 41 is
It is the main memory and has an 8-byte boundary. The memory bus 42 is a bus having a width of 8 bytes.

The RDB 43 is a buffer which temporarily holds the data read from the memory 41. The ALM 44 is an alignment that changes the arrangement of the data read from the memory 41 and sets it in the RD 45.

The RD 45 is a read register, which holds data. The MPX 46 is a multiplexer and is for writing the data of the RD 45 to the register group 47.

The register group 47 is composed of RE (even number register group) and RO (odd number register group).
4 (b). These RE, RO
Has two write ports A and B, which will be described later, and can write simultaneously.
It is possible to simultaneously write B to a total of four registers.

Next, referring to FIG. 15, data is read from the memory 41 having an 8-byte boundary, and the register group 4 is read.
The situation when writing to 7 will be described. (A) When the start address is an 8-byte boundary (lower 3 bits of start address = 000): First cycle: As shown in (A) on the memory of FIG. 15, the start address is 8 on the memory 41. From the beginning of the byte boundary, data ,,,,,,,,
Since it is lined up with ,, in the 8-byte boundary that can be read at once,
As shown in (A) on the RD of, the data is set in the RD and also in the RDB not shown.

Second cycle: read from RD,
,, and RE and RO on the register group 47 of FIG.
Write at the positions of ,,, respectively. at the same time,
Read the next data ,,, RD and RD
Set to B.

Third cycle: read from RD,
,, and RE and RO on the register group 47 of FIG.
Write at the positions of ,,, respectively. at the same time,
Read the next data,-,-,-, RD and RD
Set to B.

Fourth cycle: read from RD,
−, −, − Are written in the position of RE on the register group 47 in FIG. The above 1st cycle, 2nd cycle,
Details of data in the third and fourth cycles are shown in FIG.

(B) When the start address is 2 bytes ahead of the 8-byte boundary (lower 3 bits of start address =
010): 1st cycle: As shown in (B) on the memory of FIG. 15, the start address is from the second byte of the 8-byte boundary on the memory 41, and the data −, ...
,,,,, are arranged side by side, so it is possible to read at once in the 8-byte boundary-,,,
Is read out and set in an RDB (not shown).

Second cycle: read from RDB,
,, and of the ,,,, read out from the memory are taken out by the ALM, and as shown in (B) of RD of FIG. 15, the ,,, and are set in the RDB (not shown). To do.

Third cycle: read from RD,
,, and RE and RO on the register group 47 of FIG.
Write at the positions of ,,, respectively. at the same time,
Of the data read from the RDB and the data read from the memory, are extracted by the ALM, and, as shown in (B) on RD of FIG. set.

Fourth cycle: read from RD,
,, and RE and RO on the register group 47 of FIG.
Write at the positions of ,,, respectively. at the same time,
The data read from the RDB is taken out by the ALM, and is set as shown in (B) on RD of FIG.

Fifth cycle: Read from RD,
It writes in the position of RE on the register group 47 of FIG. FIG. 17 shows the details of the state of the data in the above first cycle, second cycle, third cycle, fourth cycle, and fifth cycle.

(C), (D) Similarly, when the start address is 4 bytes ahead (6 bytes ahead) of the 8-byte boundary (lower 3 bits of start address = 100 (110)).
Case): 1st cycle: As shown in (C) and (D) on the memory of FIG. 15, the start address is from the 4th byte (6th byte) of the 8 byte boundary on the memory 41, Data-,-,,,,,,,, (Data-,-,-,,,,,,,)
Since they are lined up, the −, − ,, (−, −, −,) in the 8-byte boundary that can be read at one time are read and set in the RDB (not shown).

Second cycle: read from RDB,
() And read from memory ...
Of (,,,), (,,) and are taken out by ALM, and as shown in (C) and (D) on RD of FIG. ,, (,,,) are set.

Third cycle: read from RD,
,, and RE and RO on the register group 47 of FIG.
Write at the positions of ,,, respectively. at the same time,
Of () read from RDB and (,,,) read from memory,
(,,) are taken out by the ALM, and, as shown in (C) and (D) on RD of FIG.
,,) are set.

Fourth cycle: read from RD,
,, and RE and RO on the register group 47 of FIG.
Write at the positions of ,,, respectively. at the same time,
The data read out from the RDB is taken out by the ALM, and as shown in (C) and (D) on RD of FIG. 15, is set.

Fifth cycle: Read from RD,
It writes in the position of RE on the register group 47 of FIG. FIG. 18 is a detailed view (C) and FIG. 19 is a detailed view (D) of the data in the first, second, third, fourth, and fifth cycles.

FIG. 20 shows a conventional operation instruction explanatory diagram. (000): Corresponding to (A) described above, details are shown in FIG. (010): Corresponding to (B) described above, details are shown in FIG.

(100): Corresponding to (C) described above, details are shown in FIG. (110): Corresponding to (D) described above, details are shown in FIG. Here, as described above, (000) and the like represent the lower 3 bits of the start address, and the memory 41 has an 8-byte boundary.

(1) In the case of (000) (when the start address is the beginning of the 8-byte boundary): S1 sets the counter CT = the number of transfers-1. Here, since the number of transfers is 9, CT = 9-1 = 8.

At S2, the processing of RQ CT <4 CT-4 is performed. That is, it is determined whether the CT calculated in S1 is smaller than 4 (CT <4), and a value obtained by subtracting 4 from CT is set as a new CT value (CT-4).

When CT <4 is determined in S2,
Since it was found that the number of data to be written in the register group is 4 or less, the data can be written in the register group in one write, so R is performed in S4.
W (write to the register group), and the process ends.

When CT ≧ 4 is determined in S2,
Since the number of data to be written in the register group is 5 or more and it is determined that the writing is required plural times, the process proceeds to S3. S3 performs the process of RW RQ CT <4 CT-4. That is, after writing four pieces of RD data to the register group, it is determined whether CT is smaller than 4 (CT <4), and a value obtained by subtracting 4 from CT is set as a new CT value (CT -4).

When CT <4 is determined in S3,
Since it was found that the number of data to be written in the register group is 4 or less, the data can be written in the register group in one write, so R is performed in S4.
W (write to the register group), and the process ends.

When CT ≧ 4 is determined in S3,
Since it is found that the number of data to be written in the register group is 5 or more and it is necessary to write a plurality of times, S3 is repeated. As a result, the data is written in the register group as shown in FIG. 15A and FIG.

Similarly, (010), (100), (11)
0) is also subjected to the illustrated process, and the data is transferred to the register group 47 as shown in FIGS. 15B and 17, FIG. 15C, FIG. 18 and FIG. Write in.

Summarizing the results described above, the following number of cycles shown in FIG. 21 (a) is required. Address lower 3 bits RS (start register) = even RS = odd 000 3 3 010 4 4 100 4 4 110 4 4 In addition, when writing to N register groups, FIG.
The number of cycles is as shown in (b).

[0032]

When the write processing is performed on the register group under the above-mentioned conventional configuration, there are the following problems.

(1) Since the number of write ports is 4, the control becomes complicated. This is because the control becomes more complicated as the number of write ports in the register group is larger, so that the control becomes more complicated when it is applied to a computer system in which the register width is doubled. Therefore, a configuration with a small number of ports is desired.

(2) If the start address is not the 8-byte boundary, there is a problem that an extra cycle is required before writing is possible. That is, since it is possible to write up to four lines, if it is not an 8-byte boundary, an extra cycle is required to read data from the memory twice consecutively and write data for four lines into the register group collectively.

The present invention solves these problems.
The purpose is to reduce the number of execution cycles by reducing the number of write ports by grouping register groups and adopting a configuration for writing to the register group even if the start address is not 8-byte boundary.

[0036]

FIG. 1 shows a block diagram of the principle of the present invention. In FIG. 1, a memory 1 is a memory that reads and writes data in boundary units.

The buffer RDB temporarily stores the data read from the memory 1 in boundary units. The alignment ALM is the data read from the memory 1 in boundary units and the buffer RD if necessary.
From the data immediately before being read from B, data corresponding to an even or odd specified start register number to be written in the registers of the register group 2 is extracted and arranged.

The register RD is a register for storing the data arranged by the alignment ALM. The register group 2 is a group of registers to be written from the position where the designated start register number is even or odd.

[0039]

The present invention, as shown in FIG.
Based on the data read by the LM in the boundary unit from the memory 1 and the data in the boundary unit of the memory 1 immediately before read from the buffer RDB as necessary, the specified start register number to be written in the register of the register group 2 is even or Extract the data corresponding to odd numbers and arrange it,
After writing this to register RD, register RD
The data read from is written from the register at the position where the specified start register number of the register group is even or odd.

Further, the register group 2 is composed of a plurality of 4-byte registers, and this register has two write ports, and a total of 8 bytes of data are simultaneously written from these two write ports.

Therefore, it is possible to reduce the number of write cycles by reducing the number of write ports by grouping the register group 2 and writing a part of the write address to the register group 2 even if the start address is not 8-byte boundary. It will be possible.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 2 is a diagram for explaining the operation of the present invention. Figure 2
(A) shows an operation flowchart. Figure 2 (a)
In S1, the counter CT = the number of transfers-the number of RWFs-1 is calculated. Here, the number of transfers is the number of transfers and writes from the memory to the register group 2, and is, for example, 9 (from 9) in the example of FIG. 3 described later. The number of RWFs is the number of lines to be written at the first time, and for example, the lower 3 bits of the example of FIG.
In the case of 0), there are four. Therefore, (00
In the case of 0), counter CT = 9-4-1 = 4.

In S2, the operation code branches. This is determined by whether the start register number = RS written in the register of the register group 2 is even or odd, and the number of transfers, as shown in the operation code branching in FIG. In the example of FIG. 3 described above, since the number of transfers = 9 and RS = even, the operation code branch (01) occurs, and the process proceeds to S3. On the other hand, in the case of the operation code branch (00), the writing of the data to the register group 2 is completed with one RW in S6.

At S3, the process of RWF RQ CT <4 CT-4 is performed. That is, after writing the data (one of 1 to 4) stored in the RD to the register group for the first time (RWF), it is determined whether CT is smaller than 4 (CT <4). , And the value obtained by subtracting 4 from CT are set as new CT values (CT-4). Where RW
In the case of FIG. 3A, F writes the four data stored in the RD for the first time to the register group 2.

When CT <4 is determined in S3,
Since it was found that the number of data to be written in the register group 2 is 4 or less and the data can be written in the register group 2 by one writing, S5
Then, RW is performed (writing to the register group 2), and the process ends.

When CT ≧ 4 is determined in S3,
Since the number of data to be written in the register group is four or more and it is determined that the writing is required plural times, the process proceeds to S4. S4 performs the process of RW RQ CT <4 CT-4. That is, after writing the data stored in the RD to the register group to the register group (RW), the CT becomes 4
Is smaller than (CT <4), and a value obtained by subtracting 4 from CT is set as a new CT value (CT-4). Here, in the case of FIG. 3A, RW is the second RD.
The four pieces of data, which are stored in, are written in the register group 2.

When CT <4 is determined in S4,
Since it was found that the number of data to be written in the register group 2 is 4 or less and the data can be written in the register group 2 by one writing, S5
Then, RW is performed (writing to the register group 2), and the process ends.

When CT ≧ 4 is determined in S3,
Since it is found that the number of data to be written in the register group is 5 or more and it is necessary to write a plurality of times, S4 is repeated. S5 is R
W (write RD data to register group 2).

As described above, the data read from the memory 1 in the boundary unit for the first time and stored in the register RD is read in S3 and stored in the register group 2. Then, after the second time, in S4, four data are written to the register group 2 by four, and when four or less data remain in the RD at last, the remaining data are written in the register group 2 in S5.

FIG. 2B shows the operation code branch.
As described above, this is the explanatory diagram of FIG.
The condition of whether to branch to the operation code branch (00) or (01) of 2 is set. Here, the number of transfers represents the number of data transferred from the memory 1 to the register group 2 (nine in the example shown in FIG. 3 and below). RS = Even (RS = Odd)
Indicates that the start register number to be written by the register group is even (odd).

FIG. 2C shows the number of RWFs. This RWF number represents the number read from the memory 1 and stored in the register RD for the first time. The lower 3 bits of the address represent the lower 3 bits of the address read from the memory 1.

In the following, the case where the number of transfers = 9 and the boundary of the memory = 8 bytes will be sequentially described in detail as an example. Figure 3
Shows an embodiment of the present invention (RS = even, lower 3 bits of address = (000), (110)).

FIG. 3A shows how data is stored in the memory 1. In FIG. 3A, (A)
Indicates that the address for reading data from the memory 1 is (00
0), the 8-byte boundary has (,,,), (,,,),
It is stored as (, −, −, −).

(D) is the case where the address for reading data from the memory 1 is (110), and the 8-byte boundary is (-,-,-,), (,
,,), (,,,) are stored.

FIG. 3B shows the state of storing in the register RD. In (b) of FIG. 3, (A) stores in the RD as follows:,: 1st cycle,:,: 2nd cycle: 3rd cycle (details are shown in FIG. 7).

(D) is stored in RD as −, −, −, −: 1st cycle:,: 2nd cycle ,,: 3rd cycle: 4th cycle (see FIG. 10 for details). Shown).

FIG. 3C shows the state of writing to the register group. In FIG. 3C, in FIG. 3A, the data on RD is written in the register group sequentially from the beginning as shown because RS = even. (D) is
Similarly, the data on RD is written with a delay of one cycle.

As described above, the lower 3 bits of the address (0
00) (A) and lower 3 bits of address (110)
In the case of (D) of FIG.
After storing in D, the data of this register RD is written in the register group 2 as it is.

FIG. 4 shows an embodiment of the present invention (RS = even, lower 3 bits of address = (010), (100)).
FIG. 4A shows how data is stored in the memory 1.

In FIG. 4A, FIG. 4B shows the case where the address for reading data from the memory 1 is (010), and the 8-byte boundary is as shown in the figure.
(-,,,), (,,,), (,,
-,-) Are stored.

(C) is a case where the address for reading data from the memory 1 is (100), and the 8-byte boundary is (-,-,), (,
,,), (,,,-) are stored.

FIG. 4B shows a state of storing in the register RD. In (b) of FIG. 4, (B) stores in RD such as −, − ,,: 1st cycle ,,: 2nd cycle ,,: 3rd cycle (details are shown in FIG. 8). ).

Similarly, RD is stored in RD in the following manner: −, − ,,: 1st cycle ,,: 2nd cycle ,,: 3rd cycle (details are shown in FIG. 9).

FIG. 4C shows the state of writing to the register group. In (c) of FIG. 4, (B) sequentially writes the data on RD to the register group from the beginning as shown below because RS = even here.

1st time :, 2nd time: ,,, 3rd time: ,, By the above, the address lower 3 bits (010) (B) and the address lower 3 bits (100) (C)
In this case, as shown in FIG. 4 (b), after being stored in the register RD, the data in this register RD is directly written into the register group 2.

FIG. 5 shows an embodiment of the present invention (RS = odd, lower 3 bits of address = (000), (010)).
FIG. 5A shows how data is stored on the memory 1.

In FIG. 5A, (A) shows the case where the address for reading data from the memory 1 is (000), and the 8-byte boundary is as shown in the figure.
(,,,), (,,,), (,-,
-,-) Are stored.

(B) is a case where the address for reading data from the memory 1 is (010), and the 8-byte boundary is (-,,,), (,
,,), (,,-,-) are stored.

FIG. 5B shows the state of storing in the register RD. In (b) of FIG. 5, both (A) and (B) are stored in RD in the following manner:-,, :: 1st cycle ,,:, 2nd cycle ,: 3rd cycle.

FIG. 5C shows the state of writing to the register group. In both (A) and (B) of FIG. 5C, the data on RD is stored in the register group, where RS =
Since it is strange, the data is sequentially written from the second as shown.

As described above, the lower 3 bits of the address (0
00) (A) and lower 3 bits of address (010)
In the case of (B) of FIG.
After storing in D, the data of this register RD is written in the register group 2 as it is.

FIG. 6 shows an embodiment of the present invention (RS = odd, lower 3 bits of address = (100), (110)).
FIG. 6A shows how data is stored on the memory 1.

In FIG. 6A, FIG. 6C shows the case where the address for reading data from the memory 1 is (100), and the 8-byte boundary is as shown in the figure.
(-,-,,), (,,,), (,,
, −) Are stored.

(D) is the case where the address for reading data from the memory 1 is (110), and the 8-byte boundary is (-,-,-,), (,
,,), (,,,) are stored.

FIG. 6B shows how the data is stored in the register RD. In (b) of FIG. 6, both (C) and (D) are stored in RD such as −, −, − ,: 1st cycle,:,: 2nd cycle ,, :: 3rd cycle.

FIG. 6C shows the state of writing to the register group. In FIG. 6C, in both (C) and (D), the data on RD is stored in the register group, where RS =
Since it is strange, the data is sequentially written from the second as shown.

As described above, the lower 3 bits of the address (1
00) (C) and lower 3 bits of address (110)
In the case of (D) of FIG.
After storing in D, the data of this register RD is written in the register group 2 as it is.

FIG. 7 shows an overall time chart of the present invention (RS = even, lower 3 bits of address = 000).
This explains the details of (A) of FIG. 3 described above. Μ is a microcode and represents the operation of FIG. 2 described above.

The request represents a memory read request (N, N + 1, N + 2) to the memory 1. The read data is the data read from the memory 1.

RDB is data temporarily stored in the buffer RDB of FIG. RD is the data stored in the register RD of FIG. -Register group shows how data is written in the register group 2 of FIG.

FIG. 7 shows the case where RS = even and the lower 3 bits of the address are (000). FIG. 8 shows an overall time chart of the present invention (RS = even, lower 3 bits of address = 010). This is described above with reference to FIG.
In the case where RS = even and the lower 3 bits of the address are (010).

FIG. 9 shows an overall time chart of the present invention (RS = even, lower 3 bits of address = 100).
This is a description of the details of (C) of FIG. 4 already described, where RS = even and the lower 3 bits of the address are (100).
It is the case of.

FIG. 10 shows an overall time chart of the present invention (RS = even, lower 3 bits of address = 110).
This is a description of the details of (D) of FIG. 3 already described, where RS = even and the lower 3 bits of the address are (110).
It is the case of.

FIG. 11 shows a flowchart of the present invention when RS = even and the number of writes = 9. This is a summary of the results of FIGS. 3 and 4 described above, and FIGS. 7 to 10 describing the details thereof.

Cycles 1, 2, 3, 4, 5 are the number of cycles for processing.・ (000), (010), (100), (110)
Represents the lower 3 bits of the address for reading data from the memory. Here, the memory has an 8-byte boundary.

In the case of (000), as shown in the figure, cycle 1: RD write ,, cycle 2: register write, cycle 3: register write, cycle 4: register write, Register write is completed in a total of 4 cycles, such as −, −, −. Similarly, (010) and (100) also complete the register write in a total of 4 cycles. In the case of (110), the register write is completed in a total of 5 cycles.

FIG. 12 shows a flow chart when RS = odd and the number of writes = 9 according to the present invention. This is a summary of the results of FIGS. 5 and 6 described above. -Cycles 1, 2, 3, 4, and 5 are the number of cycles for processing.

(000), (010), (100),
(110) represents the lower 3 bits of the address for reading the data from the memory. Here, the memory has an 8-byte boundary.

In the case of (000), since RS = odd, as shown in the figure, cycle 1: RD write,-, cycle 2: register write,-, cycle 3: register write, , Cycle 4: Register write ...,-,-In this way, register write is completed in a total of 4 cycles. Similarly, (010), (100), and (110) also complete the register write in a total of 4 cycles.

FIG. 13 shows an example of the number of cycles of the present invention.
FIG. 13A shows the case of the number of cycles of the present invention (the number of transfer sills = 9). This is RS = in FIG.
Even, in the case of RS = odd in FIG. 12, the number of cycles is summarized in a table. The number of cycles is as shown below.

Lower 3 bits of address RS = even RS = odd (000) 3 3 (010) 3 3 (100) 3 3 (110) 4 3 FIG. 13B shows the number of cycles (the number of transfer siles of the present invention. = N lines). The number of cycles is as shown below.

Lower 3 bits of address RS = even RS = odd (000) N / 4 (N + 1) / 4 (010) (N + 2) / 4 (N + 1) / 4 (100) (N + 2) / 4 (N + 3) / 4 (110) (N + 4) / 4 (N + 3) / 4

[0094]

As described above, according to the present invention,
The data read from the memory 1 in the boundary unit is stored in the buffer RDB, and the data in the boundary unit and the data read from the buffer RDB are arranged and stored in the register RD in a writable form and read from the register RD. Since the configuration that repeatedly writes data to the register group 2 is adopted, the register group 2
In addition to reducing the number of write ports, a part of the write address can be written to the register group 2 even if the start address is not, for example, an 8-byte boundary, the number of execution cycles can be shortened, and the number of write ports can be reduced. It can be reduced to simplify the process. These have the following effects.

(1) In the case of the embodiment of the present invention, the number of write ports is only 2 and it is possible to reduce the number of ports from 4 in the conventional example of FIG. 14 to half and double the register width. Therefore, it is possible to support a new architecture in which the register width is double the conventional one.

(2) Even if the start address for reading the data from the memory is not the 8-byte boundary, no extra request is required until the data can be written, and the data is written to the register group according to the data obtained by the first read. The number of execution cycles can be reduced by changing the number dynamically, suppressing unnecessary requests.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is an operation explanatory diagram of the present invention.

FIG. 3 is an embodiment of the present invention (RS = even, lower 3 bits of address = 000, 110).

FIG. 4 is an embodiment of the present invention (RS = even, lower 3 bits of address = 010, 100).

FIG. 5 is an example of the present invention (RS = odd, lower 3 bits of address = 000, 010).

FIG. 6 is an embodiment of the present invention (RS = odd, lower 3 bits of address = 100, 110).

FIG. 7 is an overall time chart of the present invention (RS = even, lower 3 bits of address = 000).

FIG. 8 is an overall time chart of the present invention (RS = even, lower 3 bits of address = 010).

FIG. 9 is an overall time chart of the present invention (RS = even, lower 3 bits of address = 100).

FIG. 10 is an overall time chart of the present invention (RS = even,
Address lower 3 bits = 110).

FIG. 11 is a flowchart of the present invention when RS = even and the number of writes = 9.

FIG. 12 is a flow chart when RS = odd and the number of writes = 9 according to the present invention.

FIG. 13 is an example of the number of cycles of the present invention.

FIG. 14 is a configuration diagram of a conventional technique.

FIG. 15 is an explanatory diagram of a conventional technique.

FIG. 16 is a conventional overall time chart (RS = even, lower 3 bits of address = 000).

FIG. 17 is a conventional entire time chart (RS = even, lower 3 bits of address = 010).

FIG. 18 is a conventional entire time chart (RS = even, lower 3 bits of address = 100).

FIG. 19 is a conventional overall time chart (RS = even, lower 3 bits of address = 110).

FIG. 20 is a diagram illustrating a conventional operation instruction.

FIG. 21 is an example of a conventional cycle number.

[Explanation of symbols]

 1: Memory 2: Register group RDB: Buffer RD: Register ALM: Alignment

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Ogura 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Toru Watanabe, 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Takumi Takeno 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Fujitsu Limited (72) Inventor, Katsunori Takeshita 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited

Claims (2)

[Claims] 1. A buffer RDB for temporarily holding data read from a memory (1) in a boundary unit in a register write system for writing data read in a boundary unit of a memory from an even or odd position in a register. , The specified start register number to be written to the register of the register group (2) corresponds to an even number or an odd number from the data read from the memory (1) in boundary units and the data immediately before read from the buffer RDB as necessary. Alignment ALM for extracting and arranging data
And a register RD for storing the data arranged by the alignment ALM, and a register group (2 which is a group of registers for writing the data read from the register RD from the position where the designated start register number is even or odd. ) And a register write method characterized by having. 2. The register group (2) comprises a plurality of 4-byte registers, the registers having two write ports, and a structure in which a total of 8 bytes of data is simultaneously written from the two write ports. Features and Claim 1
Register write method described.