JPH0238964B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to instruction execution control of an information processing device,
In particular, the present invention relates to an improved control method for storage device access in instruction execution using a pipeline control method.

A pipeline control method for executing instructions in an information processing device is well known as a control method for simultaneously executing a plurality of instructions in parallel.

In a pipeline control method, each of multiple stages connected in series to form a pipeline generally performs a different function that is part of instruction execution, and by passing through these stages in sequence, , the required instruction execution is completed.

At each stage, partial executions for different instructions are generally executed in parallel, so the entire pipeline can logically be thought of as having multiple processing flows proceeding in parallel, each of which (pipe line) flow.

Since the stages of the pipeline are serial, if a certain stage takes a long time to execute, the progress of subsequent processing is suppressed by the stage that takes a long time to execute.

[Conventional technology]

Therefore, when designing a pipeline, it is necessary to avoid significant differences in the execution time of each stage. Undesirable latencies may occur for flows that are at a stage subsequent to a read flow or a stage that is a particularly long flow (eg, a divide instruction).

FIG. 2a is a block diagram showing the configuration of a storage access control section that processes storage access requests issued from the pipeline flow of the instruction control section.

The storage address in the storage access request is set in the address register 10, the address is converted by the address conversion circuit 16, and access to the buffer 11 is first attempted.

At the same time, the address is also input to the access exception checking unit 12, and the validity of the access execution is verified by comparing, for example, the memory protection key set for the address with the access key assigned to the program being executed. A check is performed and the result is set in the exception information register 13.

If data at the requested address of the buffer 11 is stored, the data is read out and set in the data register 14, and the data is read out and set in the data register 14.
The contents of the exception information register 13 are transferred to the instruction control unit and used for instruction execution. However, if there is information indicating an illegal access in the exception information register 13, normally, for example, an interrupt is generated to interrupt instruction execution.

If there is no data at the requested address in the buffer 11, send the address in the address register 10 to the main memory 15 to start the access operation, store the read data in the buffer 11, and then repeat the same process as above. Accessing the buffer 11 completes the processing of the access request.

In this way, when accessing the main storage device 15, the access time is considerably longer than when the access ends at the buffer 11, but since the requesting flow cannot proceed unless data is obtained, it is difficult for the subsequent flow to proceed. Progress also stops and a memory access wait occurs.

FIG. 2b is a diagram showing the timing of such a waiting state.

The symbols shown in the instruction control section in the figure each represent the function of one stage of the pipeline, where D is instruction decoding, A is operand address calculation, T is address translation, B is operand data read from the buffer, and E is Operation execution, W indicates each stage of writing processing result data (however,
At T and B, an access request is issued to the storage access control unit, and the control unit executes address translation and buffer access, as described below.

In the diagram, horizontal symbol strings indicate the stages that one flow (each indicated by ~) occupies as processing progresses, and consecutive symbols indicating the same stage indicate that the symbol remains at the same stage. The processing time for that stage is long, or the previous stage is not available and is waiting.

Each vertical column represents a stage occupied by a different flow that is in the pipeline at the same time.

Further, in the pipeline of the storage access control unit in the figure, the symbol P indicates selection of a storage access request issued from the instruction control unit, T indicates address translation, B indicates buffer read, and ~ indicates the flow with the same number in the instruction control unit. handle.

If the data is in buffer, P-T-B
The access is completed by the process of , but if the target data is not in the buffer as a result of this process, for example, the main memory is accessed (part starting from time 1 in the figure) and the data is imported into the buffer. After that, the access is completed at time 2 by P-T-B processing again.

During this time, the access requests of other flows are made to wait, and the flow stops at the T stage and the flow stops at the A stage, and at time 3, the access request of the flow is accepted by the storage access control unit.

In this way, if the flow and the flow's access request also require access to main storage, the flow's access request is A at time 4.
Although the stage has been advanced and started, its completion is delayed until time 5.

[Problem that the invention seeks to solve]

As mentioned above, conventionally, main memory access requests for each flow are processed serially in time, so if access requests are made consecutively, the waiting time becomes extremely large and the effective instruction processing capacity is reduced. There was a problem.

[Means for solving problems]

The above-mentioned problem is an information processing device that has a plurality of processing stages, and uses a pipeline control method to execute control of a plurality of instructions that sequentially transition through the processing stages in parallel, A first shift register, a second shift register, a counter, a data register group, an exception register group, a buffer memory, and an access exception checking section are provided, and the first shift register , N registers are sequentially connected, and are stepped in synchronization with the transition of the processing stage of the pipeline. The counter is configured to increment in cycles and make one round in the access time of the main memory, and the counter generates a flow identification number for each main memory access request, and the counter generates a flow identification number at the beginning of each of the first and second shift registers. The data register group and the exception register group each have N registers, and are selected by the flow identification number to hold the input register at a predetermined position in the second shift register. Then, the register to be output is selected by the flow identification number at a predetermined position of the first shift register, the data read from the buffer memory is held in the data register group, and the data read out from the buffer memory is held in the exception register group. The storage device access control of the present invention is connected to hold information generated by the access exception checking unit and is configured to process storage device access requests of up to N flows on the pipeline in parallel. Solved by method.

[Effect]

Corresponding to each flow flowing through the pipeline, multiple sets of registers are provided to hold read data from the storage device and access exception information, and these registers are assigned a flow identification number assigned to each flow. so that they can be accessed separately.

With this configuration, data can be acquired in advance by processing multiple access requests in parallel, asynchronously with the pipeline progress of the instruction control unit, up to the number of accesses that are functionally possible for the storage device. Since it is possible to prevent inconsistency from occurring even if the flow is changed, it is possible to significantly reduce the access waiting time for each flow.

〔Example〕

FIG. 1a is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 1b is a control timing diagram thereof.

The storage address of an access request issued from a certain flow of the instruction control unit is set in the address register 10 in the same manner as described above, and is converted to a real storage address by the address conversion circuit 16.
Access to buffer 11 is attempted.

At the same time, the flow identification number generated by the counter circuit 20 is stored in register 22-1 and register 2.
It is set to 3-1.

The counter circuit 20 is, for example, a counting circuit that repeatedly counts at a period equal to the maximum number of flows in which memory accesses are simultaneously proceeding.

The flow identification number in register 22-1 is shifted to register 22-2 in the next cycle (T cycle described above). The register 22-2 is further connected in series to the registers 22-3 to 22-m and 22-1 to form a circular shift register. The length of this shift register is shifted every cycle so that it completes one cycle in the access time of the main storage device 15.

If the desired data is in Batsuhua 11,
The data register group 24 is read in the same manner as above.
is set in the register selected by the flow identification number of register 22-2. At the same time, exception information is set in the register selected by the flow identification number of register 22-2 in exception register group 25.

Register 23-1 is connected to registers 23-2, 23-
For example, a three-stage shift register is configured, each stage corresponding to the A, T, and B stages of the pipeline stage of the instruction control section, and shifted as each flow identification number progresses.

The flow identification number shifted to the register 23-3 in this way is used for control to select one register to be output from the data register group 24 and the exception register group 25, and the selected output is sent to the instruction control unit. It is sent to the E stage of the pipeline and processed as before.

FIG. 1b explains the timing of the above operations using the same symbols as in FIG. 2b.

Similarly to the above, the access request issued from the flow ~ is accepted every cycle and the access to the main storage device 15 is activated.
Access operations to the main memory proceed in parallel, and the access wait time for flows is significantly shortened.

In this embodiment, since the configuration is such that up to three requests are processed in parallel, acceptance of flow access is delayed until the flow access is completed.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in instruction execution using the pipeline control method,
Since the stagnation of the pipeline flow due to waiting for access to the main memory is significantly improved, there is a significant industrial effect of improving the performance of the processing device.

[Brief explanation of drawings]

FIG. 1 is a configuration and timing diagram of a storage access control section according to an embodiment of the present invention, and FIG. 2 is a conventional configuration and timing diagram. In the figure, 10 is an address register, 11 is a buffer, 12 is an access exception checker, 13 is an exception information register, 14 is a data register, 15 is a main memory, 20 is a counter circuit, and 22-1 to 2
2-m, 23-1 to 23-3 are registers, 24 is a data register group, and 25 is an exception register group.

Claims (1)

[Scope of Claims] 1. An information processing device that has a plurality of processing stages, executes control of a plurality of instructions that sequentially transition through the processing stages in parallel using a pipeline control method, and When processing a main memory access request generated from the stage, a first shift register, a second shift register, a counter, a data register group, an exception register group, a buffer memory, and an access exception checking section are provided, and the first shift register The second shift register is formed by sequentially connecting N registers, and is stepped in synchronization with the transition of the processing stage of the pipeline, and the second shift register is formed by sequentially connecting a plurality of registers, and the second shift register is formed by sequentially connecting a plurality of registers. The counter is configured to increment in the control cycle and complete one cycle in the access time of the main memory, and for each main memory access request, the counter
Generate a flow identification number and set it in the register at the beginning of each of the first and second shift registers, and each of the data register group and the exception register group has N registers, and the input register is The flow identification number held at a predetermined position in the second shift register is selected, and the register to be output is selected by the flow identification number held at a predetermined position in the first shift register. The data read from the buffer memory is held in a register group, and the exception register group is connected to hold information generated by the access exception checking unit, and storage device access of up to N flows on the pipeline is performed. A storage device access control method configured to process requests in parallel.