JPH02212952A - Memory access control system - Google Patents

Abstract

PURPOSE:To realize the security protection of stored contents through the simple constitution of a device by providing a ring buffer which is installed between a system bus and a memory and converts data according to bit shift quantity to be set by a prescribed control signal. CONSTITUTION:As for the memory 15, the data is written and read to/from it through the system bus 11 by the control of a processor 13. The ring buffer 17 is installed between the system bus and the memory, and converts the data according to the bit shift quantity to be set by the prescribed control signal. Then, the write-in or the read-out of the data to/from the memory 15 is executed through the ring buffer 17 to which the bit shift quantity of the data is set according to the prescribed control signal. Thus, the conversion of the data is executed through the simple constitution, and the security of the stored contents can be realized.

Description

[Detailed Description of the Invention] (Summary) Regarding a memory access control method effective for protecting memory contents, the purpose is to realize security protection of storage contents with a simple device configuration. In a memory access control system for memory in which data is written and read under the control of a processor, a ring installed between the system bus and memory that converts data according to the amount of bit shift set by a predetermined control signal. Configure with buffers.

[Industrial application field]

The present invention relates to a memory access control method effective for protecting memory contents.

In recent years, with the expansion of computer networks, protection of stored contents has become an important issue, and there is a need for security techniques that are particularly effective in protecting contents during reading.

[Conventional technology]

In conventional memory access control methods, an access control circuit is installed in the memory that allows reading only when synchronized with a predetermined read cycle, or decoding is made possible by central processing unit (CPU) calculations. The confidentiality of stored contents is protected using methods such as

It is configured to convert data according to a bit shift amount set by a predetermined control signal.

[Problem to be solved by the invention]

By the way, security protection using such conventional methods cannot necessarily meet the demands such as increasing the size of the device and making it difficult to perform high-speed processing when the processing procedure becomes complicated.

An object of the present invention is to provide a memory access control method that can realize security protection of stored contents with a simple device configuration.

(Means for solving problems) FIG. 1 is a block diagram of the principle of the present invention.

In the figure, data is written into and read from a memory 15 under the control of a processor 13 via a system bus 11.

The ring buffer 17 is a system bus and a memory [Operation] The present invention writes data to or reads data from the memory 15 via the ring buffer 17 in which the bit shift amount of data is set according to a predetermined control signal. By doing so, data conversion can be performed with a simple configuration, and the security of stored contents can be ensured.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of a ring buffer that implements the memory access control method of the present invention.

Here, an example of a configuration using an n-stage ring buffer is shown for a case where the data size is 27 bits.

In the figure, in the first stage ring buffer, data signal lines corresponding to 211 bits (0, 1, 2, ..., 2''-1) are connected to multiplexers 21° and 21°, respectively.
1, 21□, .

In the second stage ring buffer, the previous stage multiplexer 2
Each output signal line of 1°, 221.21g, . . . , 21g-+ is a multiplexer 22°.

22,. 22g, .

In the nth stage ring buffer, each output signal line of the previous stage multiplexer is connected to multiplexers 23° and 23°, respectively.
．． ．． 23□, .

Each control terminal C of the multiplexer 21, 22, 23 has
n-bit 91 II signal 'C, C+ "' Cm-
+J is decomposed into each bit and each bit is input. Multiplexers 21, 22, and 23 select input terminal A if C-0, input terminal B if C=1, and output terminal Y.
It is configured to be taken out.

Therefore, for example, if the data size is 16 (2') bits, the four stages of ring buffers are 1, 2, and 4 stages, respectively.
If the configuration is such that a 4.8-bit shift is possible, and the 4-bit control signal "C·C+Cm Cs J" is set to the logic shown in the table below, a shift of 0 to 15 bits can be performed.

(Margins below this page) In other words, when applying a 9-bit shift to 16-bit data, for example, by inputting the control signal "1001" to the ring buffer, the first stage ring buffer performs a 1-bit shift. The second and third stage ring buffers output the previous stage bit data as is, and the fourth stage ring buffer shifts it by 8 bits, making it possible to shift a total of 9 bits.

In this way, the ring buffer can periodically shift bits of data based on the amount of bit shift determined according to the control signal given as a keyword. That is, data conversion is possible with a simple configuration, and the memory can be handled in the same way as a normal bitmap memory.

Note that when reading data, it is necessary to input the same keyword as when writing into the ring buffer as a control signal.

Furthermore, by configuring a ring buffer using a multiplexer, much faster processing is possible than with a shift register that can similarly perform bit shifts.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to secure the security of the stored contents of the memory with a simple configuration and easy control procedure. In addition, the device size is small compared to the degree of security protection, and high-speed processing is possible, making it extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, and FIG. 2 is a block diagram showing the configuration of an embodiment of a ring buffer used in the method of the present invention. In the figure, 11 is a system bus, 13 is a processor, 15 is a memory, 17 is a ring buffer, and 21, 22, and 23 are multiplexers. Block diagram of the principle of the present invention Fig. 1

Claims (1)

[Claims] (1) Processor (1) via system bus (11)
In the memory access control method for the memory (15) in which data is written and read under the control of 3), a bit is installed between the system bus (11) and the memory (15) and is set by a predetermined control signal. A memory access control system characterized by comprising a ring buffer (17) that converts data according to a shift amount.