JPS60178539A - By-pass control system of information processor - Google Patents

Abstract

PURPOSE:To supply input data used for address calculation through a by-pass from an operand address holding circuit for a leading instruction in case of register interference by utilizing a circuit which calculates and holds an operand address. CONSTITUTION:When the leading instruction (a) is a low-address instruction, etc., an instruction (b) is not interlocked as shown in a time chart in a figure even if values in registers for base modification and index modification corresponding to the operand address of the leading instruction (a) coincide with each other. Address calculation is carried out at the stage A of the instruction (a), and data on the calculation result is by-passed immediately for the address calculation of the instruction (b) to calculate the operand address of the instruction (b). Further, an existent working address register for holding the by-passed data is utilized and an increase in hardware amount is reduced.

Description

[Detailed description of the invention]

(A) Technical Field of the Invention The present invention relates to a bypass control method in an information processing device, and in particular, to a bypass control method in an information processing device, in particular, when register interference with input data for address calculation occurs in pipeline processing, operand
The present invention relates to a bypass control method in an information processing device that bypasses address data to reduce disturbances in pipeline processing and improve instruction processing performance. (B) Prior Art and Problems In pipeline processing in an information processing device, processing of a subsequent instruction is started before the preceding instruction is completed, but the registers that are changed by the preceding instruction are changed by the subsequent instruction. When referencing, so-called register interference occurs, so processing must be started after waiting for the completion of the preceding instruction. FIG. 1 is an explanatory diagram of an example of an instruction flow, and FIGS. 2 and 3 are time charts for explaining problems with the conventional system. For example, as shown in FIG. 1, the execution control for an instruction includes a D stage for decoding the instruction, an A stage for counting the operand address, and a T stage for converting the operand address into a real address. , a B stage that reads operands from the sofa managed by the storage control unit, and an E stage that performs arithmetic processing.
It consists of each control stage of the W stage that checks and writes the results. Each of these stages is generally independent and can be controlled in advance, and pipeline processing is performed in high-speed computers. Hereinafter, the case where the control stage described above is provided will be explained as an example, but the present invention is not limited to this. Figure 2 shows the pipeline flow in the case where there is register interference between the preceding instruction a and the succeeding instruction in the registers used for calculating the operands and pulses of the succeeding instruction in pipeline processing, and the bypass is not performed. There is. The instructions are interlocked until the execution result of the instruction a is written to the register in the W stage, and after the result is stored in the register specified by the operand, operand address calculation for the instruction is started. Conventionally, to alleviate delays caused by register interference,
For example, as shown in FIG. 3, register write data of a preceding instruction a is bypassed as register read data of a subsequent instruction to shorten the interlock period. However, when this method is used for base modification and index modification in operand address calculation, the processing time can only be reduced by one stage. (C) Object and structure of the invention The present invention aims to improve the above points,
For certain instructions, the results can be generated by the circuitry that calculates and maintains the operand addresses in conventional main memory without significantly increasing the amount of hardware. The purpose is to reduce disturbances in pipeline processing due to interference and improve processing performance in controlling instruction execution. Therefore, the bypass control method in the information processing device of the present invention

In a bypass control method for an information processing device that controls the execution of instructions, it is equipped with a circuit that calculates [/swo] and a circuit that holds the operan I address calculated by the circuit. When a match is detected between the register that stores the result and the register used to calculate the operand address of the subsequent instruction, and register interference with the input data used for address 1 calculation occurs, the preceding instruction -1- Provided that the instruction is of a type that allows the contents of the register write data to be determined by the circuit that calculates the address, the above operand address cannot be used for base modification or index modification data in the operand address calculation of the following instruction. It is characterized in that it is controlled so that it is supplied by bypassing the holding circuit. Hereinafter, embodiments will be described with reference to the drawings. 1) Embodiment of the invention FIG. 4 is a diagram for explaining the control outline of the invention, FIG. 5 is a block diagram of an embodiment of the invention, and FIG. 6 is an explanatory diagram of the matching circuit shown in FIG. 5. . In the case of the present invention, the preceding instruction a is, for example, a so-called load address (LA) instruction, which determines the data to be written into the register by just calculating the address and without accessing the buffer storage. In this case, even if the result storage register of the preceding instruction a and the register of the base modification and index modification at the operand address of the succeeding instruction match, the result storage register of the preceding instruction a matches the register of the base modification and index modification at the operand address of the succeeding instruction, as shown in the time chart of FIG. , do not interlock commands. When address calculation (loading to the result storage register) is performed in the A stage of instruction a, the data resulting from the calculation is immediately bypassed for address calculation of the instruction, and the operand address of the instruction is found. The present invention is realized, for example, by a circuit configuration as shown in FIG. In FIG. 5, 1 is an instruction register, 2 is a register file, 3 is an adder/subtractor for address calculation, and 4 is a register file.
is the base register, 5 is the index register, 6
are displacement registers, 7 and 8 are registers for holding operand addresses, 9 and lO are selectors, 11 is a matching circuit, 12 is a decoding section, and 13 to 17 are registers that hold register write addresses corresponding to each stage. , 18 represents the Hari-nod flag. Instruction register 1 stores instructions fetched from main memory. Instructions can be, for example, operation codes (
OP), the first operand (OPRl), and the second operand (OPR2), and in the case of a LOAD type instruction,
The first operand is the operand to be written, and the second operand is the operand to be referenced. The second operand is defined in this example by base register number B2, index register number X2, and displacement D2. The register file 2 is a storage circuit consisting of a group of registers such as general purpose registers and floating point registers. The address calculation adder/subtractor 3 performs addition/subtraction based on input data from the base register 4, index register 5, displacement register 6, or operand address holding register 7.8 to calculate the operand address. It is a circuit. Adder/subtractor 3 for address calculation
The operand address calculated by is supplied to valid address holding register 7 or 8. Note that the operand address holding registers 7.8 are conventionally provided working addresses and registers for temporarily holding and updating operand addresses in order to process variable-length operands in main memory. This register can be used to hold the bypass data of the present invention. The matching circuit 11 is a circuit that detects whether the result storage register of the preceding instruction and the register used for calculating the operand address of the succeeding instruction match. -Number circuit 1
The output of 1 causes a selection in selector 9.10. The decoding unit 12 is a circuit that analyzes the operation code of an instruction, and in particular, in the case of this embodiment, with respect to the preceding instruction, the output of the adder/subtractor 3 for address calculation determines whether the instruction can calculate the register write data. The valid flag 18 is set/reset. For example, if the instruction is at the load address (LA)
When the instruction is such that a result can be obtained in a quick cycle of instruction processing, the ``varin 1'' flag 18 is set. When the valid flag]8 is set, a bypass control enable signal is output to the minus number circuit 11. The register write address (A1) in the A stage is stored in the register 13. In register 14,
Similarly, the register write address (
TI) is stored. The same applies to registers 15-17. - The number circuit 11 is the base matching circuit 1 as shown in FIG.
1-1, and an index-number circuit 11-2. Base matching circuit] 1-1 compares the register write address (A1) of the preceding instruction such as the LA instruction and the 13th part of the subsequent instruction, that is, the register address of the --- base modification, and determines that they match. When the data is read out from the register file 2, the contents of the register (WARI) 7, which was previously set by the preceding LA instruction, are guided to the input capo of the adder/subtractor 3 for address calculation (EAI). , bypass control.The index-number circuit 11-2 similarly handles the register write address (AI) and 1 of the subsequent instruction.
The second part, that is, the index-modified register address, is compared, and when they match, the contents of the register (WAR2) 8 are bypassed as input data to the adder/subtracter 3 for address calculation. By doing this, as shown in Figure 4,
The flow becomes a pipeline flow, and pipeline processing is performed without any disturbance. In addition, it goes without saying (,
When the address (AI) matches the base or index and the balin flag 18 is in the reset state, it can be considered that wait control similar to the conventional one is performed.In the above embodiment, the address calculation adder/subtractor 3 1.A is an instruction that can calculate register write data as an output.
Of course, the target instruction changes depending on the instruction center, and is not limited to the above example, but any instruction that can obtain a result in a fast cycle of instruction processing can be bypassed according to the present invention. It can be controlled. (E) As described in detail, according to the present invention, as can be seen from FIG. 4, the 5-cycle processing is shortened compared to the case of not bypassing at all as shown in FIG. 2, and as shown in FIG. Compared to the case of bypassing from the register write data shown in the figure, it is possible to shorten the time by 4 cycles. Further, since existing working address registers and the like that hold bypass data can be used, the amount of hardware does not need to increase much.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for an example of an instruction flow, FIGS. 2 and 3 are time charts for explaining problems with the conventional method, and FIG. 4 is a diagram for explaining an outline of control of the present invention. FIG. 5 is a block diagram of an embodiment of the present invention, and FIG. 6 is an explanatory diagram of several circuits shown in FIG. 5. In the figure, 1 is an instruction register, 2 is a register file, 3 is an adder/subtractor for address calculation, 4 is a base register, 5 is an index register, and 6 is a displacement register.
Registers 7 and 8 are operand address holding registers, 9 and 10 are selectors, 11 is a matching circuit, 1
Reference numeral 2 represents a lever 1 portion, 13 to 17 represent registers that hold register write addresses corresponding to each stage, and 18 represents a Harisodo flag. Patent applicant Fujitsu Ltd. Representative Patent Attorney Hiroshi Mori 1) (1 other person) 1m, 2m, 3 years old, 4 years old

Claims (1)

[Claims] In a bypass control method in an information processing device that controls the execution of instructions and includes a circuit that calculates an operand address and a circuit that holds the operand address calculated by the circuit, an input used for address calculation during pipeline processing When register interference with data occurs, for calculating the operand address of the subsequent instruction, provided that the preceding instruction is of a type that allows the contents of the register write data to be determined by the circuit that calculates the operand address. 1. A bypass control method for an information processing device, characterized in that the data is bypassed and supplied from a circuit holding the operand address.