JPS6297037A - Check processing system for address overlap - Google Patents

Abstract

PURPOSE:To calculate an overlapping amount at an earlier period by using a bypass route which supplies the information to an address generator by bypassing also for an overlap checker. CONSTITUTION:The information to be set to a general-pourpose register group 11 is supplied also to a bypass route 12 in case a change is produced by a pipeline advance instruction and then to an address generator 1. The information is also supplied to an overlap checker 3 through the output stages of selectors 8 and 9. As a result, the same information is supplied also to the checker 3 when the 2nd operand address is calculated by the generator 1. Thus it is possible to calculate at an earlier period the amount overlapped with the 1st operand address, i.e., the contents of a register 2.

Description

[Detailed Description of the Invention] [Summary] In a data processing device that has an address generator and an overlap checker, and performs processing while checking whether there is an overlap between a second operand address and a first operand address. , information resulting from taking into account information from the bypass route provided to the address generator in calculating the second operand address.

Supply it to the overlamp checker above.

It is disclosed that processing delays caused when the contents of a base register are changed by a pipeline preceding instruction are eliminated.

[Industrial application field]

The present invention has an address overlap check processing method, in particular, a function of performing a check using an overlap checker when performing processing such as reading and processing the contents of the second operand and storing it in the position of the first operand. The present invention relates to an address overlap check processing method that allows inputs to be supplied to an overlap checker to be prepared at an early stage in a data processing device.

[Conventional technology]

In a data processing device that performs pipeline processing, the first
An instruction that reads an operand and a second operand from main storage, performs an operation, and writes the result to the first operand location on main storage, or an instruction that reads an operand from main storage and writes the result to main storage. An instruction to write to the location of the first operand, etc., may be executed.

When executing such an instruction, the software interface condition is that operations of 1 byte, which is generally the unit of address, are executed sequentially and the result of the processing length of the instruction is finally obtained. is assumed.

However, in terms of hardware, processing is performed with a bus width of 1 word, 2 words, or 4 words, which is the maximum processing unit of the device, to reduce the number of processing times and increase speed.

In other words, in terms of hardware, we aim to increase the speed as described above,
The byte length is such that the second operand address and the first operand address do not overlap when executing the above instruction.

We are trying to make it a processing unit on the hardware. For this purpose, a configuration is being considered in which a three-input overlap check adder (overlap checker) for calculating the amount of overlap is placed in parallel with the address generator.

FIG. 3 shows the conventional configuration, and FIG. 4 shows a time chart when processing is interrupted.

In the figure, 1 is an address generator, 2 is an address holding register, 3 is an overlap checker, 4 is an index register, 5 is a base register, 6 is a displacement register, 7 to 9 are selectors, IO is an instruction register, 11 is a general-purpose register group, 1
2 represents a bypass route.

In the conventional case, the first operand address is calculated by address generator 1 and set in register 2 in the first flow, and the second operand address is calculated by address generator 1 and set in register 2 in the second flow. An overlap check is performed on the contents of the base register 5, which is a generation element that generates an operand address, and the contents of the displacement register 6.

The data is input to register 3 and checked against the contents of register 2.

Note that the base register 5 is supplied with the contents of the general-purpose register indicated by the base register specification part Bl of the instruction set in the instruction register 10, and the displacement register 6 is supplied with the displacement DI of the instruction. Supplied.

Then, in consideration of the case where the general-purpose register indicated by the base register specification part of the above instruction is changed by the pipeline preceding instruction, the second operand address can be determined early even in such a case. for,
A bypass route 12 was created and the contents of the bypass route were supplied to the address generator 1 via the selector 7.8. That is, information as a result of changes made by the pipeline preceding instruction.

The address generator 1 is supplied early via the bypass route 12.

[Problem that the invention seeks to solve]

Although the above configuration has been considered in the past, the information from the bypass route 12 is only supplied to the address generator 1 in the case shown in FIG. Not supplied. For this reason, as shown in the time chart shown in FIG. 4, when a change is made by the pipeline preceding instruction as described above,
The overlap checker 3 cannot perform a check until the result of the change is written to the general-purpose register group 11 and then reflected in the base register 5. That is, until then, an interruption occurs in order to determine the second operand address and determine the amount of overlap (the continuous portion of phase A in the second flow shown in FIG. 4 corresponds to the interruption). .

[Means for solving problems]

The present invention solves this problem, and FIG. 1 shows a basic configuration diagram of the present invention (also an embodiment configuration of the present invention). The symbols in the figure correspond to those in Figure 3, and ■ indicates the address.
Generator, 2 is an address holding register, and 3 is an overlap checker.

4 is the index register, 5 is the base register,
6 is a displacement register, 7 to 9 are selectors, 10 is an instruction register, 11 is a group of general-purpose registers,
12 represents a bypass route.

In the case of the present invention, the signal is input to the overlap checker 3 from the output stage side of the selector 8.9. For this reason, the information set in the general-purpose register group 11 is transferred to the second operand via the bypass route 12.
When supplied to address generator 1 for address calculation.

It is also supplied to the overlap checker 3 from the output stage of the selector 8.

[Effect]

When changed by the pipeline preceding instruction as described above, the information to be set in the general-purpose register group 11 is also supplied to the bypass route 12 and supplied to the address generator 1. It is also supplied to lap checker 3.

As a result, the second
When the operand address is calculated, the same information is also input to the overlap checker 3.

The amount of overlap with the first operand address (contents of register 2) can be calculated early.

〔Example〕

Since the configuration of the embodiment of the present invention is substantially the same as the principle configuration diagram shown in FIG. 1, the explanation will be continued without duplication, but with reference to the time chart of the embodiment shown in FIG.

Assuming that the first operand address is set in register 2 in the first flow, and the above change is made by the pipeline preceding instruction, the change result is applied to the second operand address calculation at the timing shown in Figure 2. The address generator 1 can be supplied to the address generator 1 via the bypass route 12, but the overlap checker 3 can perform a check at the same timing.

〔Effect of the invention〕

As explained above, according to the present invention, by simply sharing the bypass route that bypasses and supplies information to the address generator for the overlap checker,
It is possible to achieve the intended purpose. This also greatly simplifies the control mode.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is a time chart of an embodiment of the present invention, Fig. 3 is an example of a configuration based on the premise of the present invention, and Fig. 4 is a time chart for the configuration shown in Fig. 3. Show chart. In the figure, 1 is an address generator, 3 is an overlay checker, 4 is an index register, 5 is a base register, and 6 is a displacement register.

Claims (1)

[Scope of Claims] An address generator (1) that calculates an operand address, and an amount of overlap between the second operand address of the calculated result and the first operand address of the previously calculated result. In the data processing device, the address generator (1) has an overlap checker (3) that calculates the address generator (1), and has a function of executing an instruction to read at least the second operand and write the processed result to the first operand location. As inputs, the contents of the index register (4), the base register (
5), the result of selecting the content from the bypass route (12), and the content of the displacement register (6), and the overlap checker (3). As inputs, the output of the previous address generator (1), the selected result inputted to the address generator (1) at the relevant time, and the address generator (1)
1.) An address overlap check processing method characterized in that the address overlap check processing method is configured such that three contents of the displacement register (6) input at the relevant time are supplied to the address overlap check processing method.