JPS60204036A - Data processing device - Google Patents

Abstract

PURPOSE:To execute a processing without disturbing an advance control by bypassing the result of an address calculation and delivering it to the succeeding instruction, when it is detected that the result of an address generating instruction is requested by its succeeding instruction. CONSTITUTION:Register number comparing circuits 20, 21, 30 and 31 are connected to instruction registers 10-14, also the instruction of the register 10 is decoded by an instruction decoder 1, its result is set to each index and base register 70, 71, and its contents and a displacement D of the register 10 are added by a three-input adder 72 and set to a register DAR73. In such a state, it is detected by a comparator 21 or 20 that a store register of an instruction of a load address system is the same as the base or index register of the next instruction, the output line 73l of the DAR73 is selected by a selector 61 or 60, and set to the register 71 or 70.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing device that processes instructions using advance control, and particularly to a processing method for address generation instructions.

[Background of the invention]

A load address type instruction (hereinafter referred to as LA instruction), which is an address generation instruction, determines a memory address by calculating an address and stores the result in a general-purpose register (hereinafter referred to as GR). Generally, the address set by the LA instruction is used as a base value or index value in subsequent instructions.

Therefore, compared to other instructions, the result of the LA instruction is used more frequently for calculating the address of the gray instruction.

BACKGROUND ART Conventionally, in a data processing apparatus that performs advance control, a method has been adopted in which when a subsequent instruction uses the result of an instruction currently being executed, the advance operation of the subsequent instruction is prohibited.

In this method, instructions subsequent to the LA instruction are forced to wait relatively frequently, resulting in a decrease in performance.

As a solution to this problem, conventionally, when the instruction immediately following the instruction that updates the GR, including the LA instruction, requires each of the same GRO, a method was proposed in which the data before being stored in the GR was bypassed. -46170, Special Publication No. 1987
-9088 etc. The methods shown in these
In both cases, the operand is in memory, and either the operand is read from memory and the data is used as is to calculate the address of the subsequent instruction, or a dedicated pre-operation unit is used to advance the operation before the actual operation is executed. Performs an operation and uses the result to calculate the address of the subsequent instruction.

However, with these methods, the same processing occurs even in cases where memory read is not required like the LA instruction, and the result of address calculation is used as is for the address calculation of the subsequent instruction. , the subsequent commands are still served.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned drawbacks, L
It is an object of the present invention to provide a data processing device that processes the results of the I and A instructions without disturbing the preceding control when the results of the I and A instructions are used in instructions subsequent to the A instruction.

[Summary of the invention]

The present invention performs instruction processing without disturbing advance control by bypassing the result of address calculation using the LA instruction and passing it to the subsequent instruction.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 shows the instruction format. OP is the instruction code, R is the GR number indicating the first operand, X, B, D are the index register numbers for storing the second operand address,
Pace register number.

and displacement. The second operand address is determined by GR(X)+Gl-L(B)+D(G
R(i) means GEL number number content).

The LA instruction stores the second operand address in the number hole GR.

FIG. 2 is a block diagram showing one embodiment of the present invention.

Instruction registers 10-14. Instruction decoder 1. LA instruction holding flip-flops 2-5. Register number comparison circuit 20
, 21.50, 51. AND gate 20G, 21G
.

30G, 31G, and register memory 6 that constitutes GR; multiplexers 50 and 51° that independently select arbitrary OR; selectors 60 and 61° that select address calculation data; and index register 70 that holds index values. Pace register 71 which holds the base value; Three-man power adder 72 which performs address calculation. DAR 73 that holds address calculation results, main processing unit 82. Main computing unit manual register 80
,81. and a result register 86.

The basic stages of instruction processing are D, M, A, and L.
.

It consists of 6 stages: B and W. Instruction registers 10-14
correspond to stages DH, respectively. In the D stage, the decoder 1 decodes the instruction and the tooth register 1. The setting 2M stage of index register 70 is 3
Address calculation by the manual adder 72, A and L stages perform memory reading when operand reading is required, E stage performs arithmetic execution, and W stage stores results.

The processing of the LA command is shown in the time chart of FIG. 3(a). D stage is activated at stage a, and below, b-fK
M-W corresponds. In the D stage, the instruction register 10 is decoded. Selector 50.5 for X and B in parallel
1 and selects the index value and base value sent to index register 70.1 via selectors 60 and 61. Set to base register staff 1. In the M stage, the index register 70, topace register 71, and Df5 manual adder 72 of the instruction register 10 perform IJO calculation, and the result is D.
Set to AR7!1. Since the LA instruction does not read the memory, it does not read the memory in the A and L stages.

However, since the address calculation result is an operand, DA
lt73 is set in the arithmetic unit manual register 80 at the L stage. In the E stage, the contents of the main processor manual register 80 are passed through the main processor 82 and set in the result register 86. In the W stage, the contents of the result register 83 are stored in the register memory 4.

When the LA instruction is detected by the decoder 1 in the D stay, the line LA is turned on, and the line is then M.

LA ordering doctor's frig 7 corresponding to A, L, H stage
Set 0 knobs 2 to 5.

FIG. 3(b) shows an operation time chart when the result of the LA instruction is used as the base value of the next instruction.

To detect that the storage register of the LA instruction and the pace register of the next instruction are the same, a comparator 21 compares B of the instruction register 10 (next instruction) and R of the instruction register 12 (LA instruction) of stage C1d. If they match, the peak is removed from the LAA order holding flip-flop 3 and the signal 211 is turned on.

When the signal 21Jl- is on, the selector 61 selects the DAAl2O output line 7 that holds the address calculation result of the LA instruction, and sets it in the pace register 71 after stage C.

Similarly 1. When the storage register of the A instruction and the index register of the next instruction are the same, it is detected by the comparator 20,
The selector 70 selects the output line 731 of the DAR 73 based on the match signal line 20J-, and sets it in the index register 70.

FIG. 3C shows an operation time chart when the results of LA instructions are used as base values for successive instructions.

Detection that the storage register of the LA instruction and the pace register of the next instruction are the same is performed in stage e.

A comparator 61 compares B in the instruction register 10 (one instruction after another) and R in the instruction register 14 (LA instruction) of f, and if they match, the LA instruction holding flip foot 5 takes an AND and outputs a signal 51L. This is done by turning on. When the signal 51J- is on, the output line 80L of the arithmetic unit input register 80 holding the address operation result of the LA instruction
is selected by the selector 61 and set in the pace register 71 after stage e.

Similarly, when the storage register of the LA instruction and the index register of the next instruction are the same, it is detected by the comparator 60,
The selector 70 selects the output line 80i of the arithmetic unit manual register 80 using the match signal line 30J-, and sets it in the index register 70.

In this embodiment, the instruction immediately after the LA instruction is executed with a two-cycle delay, but even in a device that executes with a one-cycle delay, if the present invention is implemented in which the address calculation result is directly input to the address calculation, the subsequent instruction can be executed. It is clear that there is no need to wait.

〔Effect of the invention〕

According to the present invention, in a data processing device that performs instruction processing using advance control, when executing a load address type instruction, when the result of the load address type instruction is used in the immediately following instruction, the load address type instruction is Since the results are bypassed and set up, processing can be performed without disturbing the advance control, and there is an effect that performance does not deteriorate.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an instruction format, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIGS. 6(a) and 6(b) are time charts explaining FIG. 2. 10-14...Instruction register, 20.21.5
0, 31...Comparator, 6...Register memory, 50.51.60,61...Selector. 70.71.75, 80, 81.85...Register. 72...3 manual adder, 82...main computing unit. Representative Patent Attorney Akira Takahashi Paperback 1 Figure 2 (C) Procedural amendment (method) Indication of the case Showa, 9th year patent application No. 58259 Name of the invention Data processing device Person making the amendment 1 ton 1 lll + 4 Patent Applicant \ and i +h:
(511) l 1,4 Certification Meeting 1 1J Standing Manufacturing Agent Column 1 for a brief explanation of the drawings of the specification subject to personal amendment, page 9, line 18 of the specification, [Figure 6 is (cL ), t
h)” and “Fig. 6 (cL), 1b),”
1G) Correct it as J. that's all

Claims (1)

[Claims] In a data processing device that processes instructions using advance control, the result storage register number of the address generation instruction indicates that the instruction subsequent to the address generation instruction requests the result of the address generation instruction as a base value or index value. , a means for detecting by comparing the pace register number or index register number of the subsequent instruction, and holding the address calculation result of the address generation instruction when it is necessary to calculate the address of the subsequent instruction before the completion of the above address generation instruction. A data processing device comprising a bypass means for calculating an address of a subsequent instruction by using a register.