JPH07113891B2 - Pipeline processing equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline processing device for processing an instruction by using a pipeline, and more specifically, the data obtained by executing the instruction is passed to another instruction at high speed for processing. The present invention relates to a pipeline processing device.

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus, one instruction is divided into a plurality of stages, and when a certain instruction completes the execution of one stage, the next instruction executes the stage so that one stage is executed. The performance is improved by making the result of the instruction available at every execution time. An information processing device that performs such processing is called a pipeline processing device.

FIG. 5 shows a block diagram of a conventional pipeline processing apparatus. Here, one instruction is IF, DEC, EX, M
It is executed by dividing it into 5 stages of EM and WB. IF
The stage reads the instruction, and the DEC stage decodes the instruction and reads the register.
The EX stage performs the operation indicated by the instruction, the MEM stage accesses the memory when the instruction is a load or store instruction, and the WB stage stores the data.

In FIG. 5, reference numeral 1a is a register file including a plurality of registers. The DEC stage accesses two registers designated by an instruction and outputs data a and data b having the contents. Reference numeral 2 is an EX stage arithmetic unit, which performs arithmetic operations designated by an instruction on data a and data b
Against the EX stage. Reference numeral 4 denotes a MEM stage holding circuit, which stores the calculation result of the EX stage calculation device 2 into M
Hold temporarily on EM stage. A selection circuit 5 selects the output of the MEM stage holding circuit 4, that is, the operation result when the instruction is an operation instruction, and selects the load data 10 read from the memory device 9 when the instruction is a load instruction. To the register file 1a, and the register file 1a writes the data output from the selection circuit 5 in the WB stage. When there is data dependence between instructions, that is, when the next instruction uses the operation result of the previous operation instruction,
The operation result is given to the input of the EX stage operation device 2 via the bypass path 20, and the operation is performed with the data a or the data b read from the register file 1a. If the next operation instruction uses the data read from the memory device 9 by the load instruction as the previous instruction, the read data is given to the EX stage operation device 2 via the bypass path 21 and the data a Alternatively, the calculation is performed with the data b.

FIG. 6 shows the operation of this pipeline processing apparatus. The first instruction ADD adds the data in the registers r1 and r2 and stores the result in the register r3. Second
Instruction SUB subtracts the data in register r4 from register r3 and stores the result in register r5. The second command SUB
Register r3 read at the DEC stage is the first instruction AD
Since it is the data before being rewritten by D, the operation of the second instruction SUB must wait for the completion of the first instruction ADD. Normally, in a high-performance pipeline processing device, the operation result is obtained at the end of the EX stage.
By using the operation result immediately as the input data of the next instruction SUB without waiting for the end of the WB stage of ADD,
The second instruction SUB can be operated without waiting. Such data passing method is called bypass.

However, the third instruction LD reads the data from the memory address indicated by the register r1, stores the data in the register r2, and the fourth instruction SUB registers the data.
When the data in register r3 is subtracted from r2 and the result is stored in register r4, the data read by the LD instruction is obtained at the WB stage of the LD instruction, so even if it is immediately bypassed to the arithmetic unit, For the instruction SUB, the execution of the operation is made to wait for one cycle.

Next, as another conventional example, a pipeline processing apparatus having two arithmetic units and simultaneously executing two arithmetic instructions will be described. FIG. 7 shows its block diagram.

The register file 1b simultaneously reads the contents data a, data b, data c, and data d of the four registers required for two operations, and the data a and data b are read by the EX stage operation device 2a. c and the data d are calculated by the EX stage arithmetic unit 2b, and the results are respectively stored in the MEM stage holding circuits 4a and 4a.
b through the selection circuits 5a and 5b, the register file 1b
Stored in.

If the instruction is a load instruction, the memory device 9
The load data 10 read from is selected by the selection circuit 5a or 5b and stored in the register file 1b. If there is a data dependency between the operation instructions, the operation instructions are passed via the bypass path 20a or 20b,
If there is a data dependency between the load instruction and the operation instruction, the EX is passed via the bypass 21a or 21b.
It is given to the stage arithmetic unit 2a or 2b.

FIG. 8 is a diagram showing the pipeline operation of the pipeline processing apparatus shown in FIG. First instruction and second
Instructions have no data dependency, so they are executed in parallel.
However, since the third instruction and the fourth instruction have data dependence, the fourth operation is kept waiting until the operation of the third instruction is completed.

[0011]

As described above, in the conventional pipeline processing apparatus, if there is a data dependency between two instructions, the execution of the subsequent instruction is delayed, which causes a problem of performance degradation. there were.

The present invention has been made in view of the above problems, and provides a pipeline processing apparatus capable of reducing the time to wait for the execution of instructions when there is data dependence between instructions. With the goal.

[0013]

A pipeline processing apparatus according to the present invention comprises a first arithmetic unit for performing an arithmetic operation at an Nth stage of pipeline processing consisting of a plurality of stages, and
A second arithmetic unit for performing arithmetic in the + 1st stage;
When the data dependence detecting device includes a data dependence detecting device and a control device and detects that the data used for the operation indicated by the instruction is not in time for the operation of the Nth stage because it is updated by the previous instruction, The control device controls the second arithmetic device to perform arithmetic operations, and when the data dependence detection device detects that the data is in time for the arithmetic operation of the Nth stage, the control device performs arithmetic operations using the first arithmetic device. It is controlled to do so.

[0014]

According to the present invention, with the above configuration, the operation when there is data dependence between instructions can be performed in a stage after the operation stage when there is no dependence, so the time that is waited due to data dependence Is shortened.

[0015]

(Embodiment 1) FIG. 1 shows a block diagram of a first embodiment of the present invention.

In this figure, 2 is an EX stage arithmetic unit,
Reference numeral 3a is a MEM stage arithmetic unit, and 6 is a data dependence detecting device for holding an instruction being executed and checking whether or not there is a data dependence between these instructions when a new instruction is given.

The instruction read in the IF stage is decoded in the DEC stage, and the data a and the data b designated by the instruction are read from the register file 1a in the same DEC stage according to the decoding result. Further, the operation indicated by the instruction is executed in the EX stage by the EX stage operation device 2. The calculation result is temporarily held in the MEM stage holding circuit 4 in the MEM stage, selected by the selection circuit 5, sent to the register file 1a, and stored in the register 1a designated by the instruction in the WB stage. Reference numeral 20 is a bypass path when the operation result of the previous instruction is used by the next instruction.

When the previous instruction is the load instruction and the data read from the memory 9 is used as the input data for the operation by the next instruction, that is, the data read from the memory device 9 is the operation of the EX stage of the next operation. The data dependence detection device 6 detects that it is not in time. Data dependence detection device 6
When it is detected that the values do not match, the detection signal 7
Then, the control device 8 outputs the control signal 9 to pass the data 10 read by the load instruction to the MEM stage operation device 3a at the MEM stage of the next instruction to perform the operation.

FIG. 2 shows the pipeline operation of the pipeline processing apparatus shown in FIG. The third instruction LD is the register r
The data of the address of the memory indicated by 1 is read by the MEM stage and stored in the register r2. Fourth instruction SUB
The data read out by the third instruction LD Ri preparative received in MEM stage performs content and subtraction of the register r3 in MEM stage, and stores the result in register r4 in WB stage. Thus, the completion of the fourth instruction SUB is the same as the case where there is no data dependency.

As described above, according to the present embodiment, even if it is late to obtain the data necessary for the operation due to the data dependence between the instructions, it is possible to eliminate or reduce the delay of the instruction completion. It is possible to improve the performance of the pipeline processing device, which is extremely useful in practice.

(Embodiment 2) FIG. 3 shows a block diagram of a pipeline processing apparatus according to a second embodiment of the present invention.

Reference numerals 2a and 2b denote EX stage arithmetic devices, both of which perform arithmetic in the EX stage. 3b is a MEM stage arithmetic unit.

If there is no data dependency between instructions,
Two operations are performed every cycle using the two EX stage operation devices 2a and 2b.

When the data dependence detecting device 6 detects that there is a data dependence between instructions and the data is not in time for the operation of the EX stage, the data dependence detecting device 6 outputs a detection signal 7 to the control device 8. The control device 8
The previous instruction of the two instructions is calculated by the EX stage arithmetic unit 2a, and the result is sent to the MEM stage arithmetic unit 3b to be arithmetically operated by the MEM stage. At this time, EX
The stage arithmetic unit 2b sends necessary data of the data c and the data d to the MEM stage arithmetic unit 3b as it is. The calculation result of the MEM stage calculation device 3b is the selection circuit 5
It is selected by b and stored in the register file 1b.

FIG. 4 shows the pipeline operation in this case. The register r3 used by the fourth instruction SUB is updated by the immediately preceding third instruction ADD. In this case, the third instruction ADD
Performs an operation in the EX stage, uses the result thereof, and the fourth instruction SUB performs an operation in the MEM stage and stores the result in the register r5 at the WB stage. Thus, even if there is data dependence between two arithmetic instructions, the WB stage is completed in the same time as when there is no dependence.

As described above, according to the present embodiment, even if it becomes late to obtain the data necessary for the operation due to the data dependence between the instructions, the delay of the instruction completion is eliminated or reduced. It is possible to improve the performance of the pipeline processing device, and it is extremely useful in practice.

[0027]

As described above, according to the present invention, the delay of instruction completion can be eliminated even if it becomes late to obtain the data necessary for the operation due to the data dependence between the instructions. Alternatively, it can be reduced, and the performance of the pipeline processing device can be improved, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram of a pipeline processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation of the pipeline processing device shown in FIG. 1 in the embodiment.

FIG. 3 is a block diagram of a pipeline processing device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an operation of the pipeline processing device shown in FIG. 3 in the embodiment.

FIG. 5 is a block diagram of a conventional pipeline processing device.

FIG. 6 is a diagram showing an operation of the pipeline processing apparatus shown in FIG.

FIG. 7 is a block diagram of another conventional pipeline processing device.

FIG. 8 is a diagram showing an operation of the pipeline processing device shown in FIG. 7.

[Explanation of reference numerals] 1a, 1b register file 2, 2a, 2b EX stage arithmetic device 3a, 3b MEM stage arithmetic device 4, 4a, 4b MEM stage holding circuit 5, 5a, 5b selection circuit 6 data dependence detection circuit 8 control circuit

Claims (1)

[Claims] 1. A pipeline processing apparatus for dividing one instruction into a plurality of stages for pipeline processing, wherein: a first arithmetic unit for performing an operation on an Nth stage of the plurality of stages; A second arithmetic unit for performing an arithmetic operation on the (N + 1) th stage, a data dependence detecting unit for detecting a data dependence relation between instructions, and a control unit are provided, and the two instructions are provided for the data dependence between the two instructions. If the data dependence detecting device detects that the data required by the latter instruction of the second instruction is not in time for the Nth stage, the control device causes the second arithmetic device to perform the operation of the latter instruction. If the data dependence detecting device controls and the data required by a later one of the two instructions is in time for the Nth stage, the control device determines A pipeline processing device, characterized in that the subsequent arithmetic operation is controlled to be performed by the first arithmetic device.