JPH07191911A - Address converter and microprocessor computation method - Google Patents

Abstract

PURPOSE:To provide the address converter and the address computing method which quickly execute, the address computation consisting of address calculation and address conversion. required for memory access in a microprocessor. CONSTITUTION:In this address converter, not only a physical address corresponding to a virtual address stored in a certain virtual address storage field 115 but also physical addresses corresponding to virtual addresses obtained by adding and subtracting one to and from this virtual address are stored in a physival address storage field 125, and one of these physical addresses is selected and outputted in accordance with input of physical address select signals 1 and 2 (103-1 and 103-2). This address computing method in the microprocessor uses this address converter and performs address conversion of the lower address and that of the upper address in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor which is the core of an information processing system, and more particularly to an address calculation method required when the microprocessor reads / writes data from / to a storage device.

[0002]

2. Description of the Related Art In a conventional microprocessor,
Address calculation and address conversion are required when loading (reading) data from a storage device (hereinafter referred to as memory) and when storing (writing) data in the memory. Hereinafter, reading and writing to the memory is referred to as accessing the memory, and load instructions, store instructions, and the like used when accessing the memory are referred to as memory access instructions. The address calculation and the address conversion are collectively called address calculation.

The address calculation is a calculation for obtaining the virtual address of the memory from the information given in the memory access instruction. FIG. 9 is an explanatory diagram showing an address calculation method using a load instruction as an example. In the load instruction of FIG. 9, R5, that is, register 5 is designated as the register containing the base address. Also, as a value indicating the displacement from the base address, 100
Is specified. The virtual address of the memory to be loaded is obtained as the storage result of the register 5 and the addition result of 100. Register 4 is designated as a register for storing the loaded data. Taking the 64-bit address architecture as an example, it is usual that the base address has 64 bits and the displacement bit has 16 bits. Here, the number of bits of the displacement is 32 bits in many cases, so that the number of bits of the displacement is determined by the constraint of the number of bits included in the instruction length.

The virtual address thus obtained is converted into a physical address by address conversion. The address conversion is performed by the address conversion device. The address translation device is a TLB (Translation Look aside Buf).
fer), and often called the address translation buffer. The address translation device of the prior art uses an address of an upper part of a virtual address (hereinafter simply referred to as upper address).
And the upper address of the physical address corresponding to this are stored as a pair. The upper address of the physical address is output for the input of the upper address of the virtual address. The address of the lower part of the virtual address (hereinafter simply referred to as the lower address) is used as it is as the lower address of the physical address. Here, in the case of the 64-bit address architecture, the number of bits of the virtual address is 64 bits, and the number of bits of the lower address is often 12 to 16 bits. Therefore, the bit number of the upper address of the virtual address is 52 bits to 48 bits.
Often taken in bits. Further, the number of bits of the physical address is often set to about 48 bits. As can be seen from the above description, the number of bits of the lower address of the physical address is the same as the number of bits of the lower address of the virtual address. Since the number of bits of the lower address of the physical address indicates the size of the page which is a unit for address conversion, the size of the page is 4 Kbytes to 64 Kbytes.

FIG. 10 is a block diagram showing a part of the pipeline structure of a conventional microprocessor for explaining the processing procedure in the conventional microprocessor regarding the address calculation method consisting of the above address calculation and address conversion. Is. As shown in FIG. 10, the address calculation is first performed by the adder 1010 to obtain the virtual address. This address calculation is performed using one pipeline stage. This pipeline stage is generally called an execution stage, and is a so-called ALU (Arithmetic Logic) such as an addition instruction and a subtraction instruction.
Unit) is a pipeline stage where instructions are processed. The ALU is often used as it is for the adder 1010 itself. In the next pipeline stage, address translation is performed by address translation device 1030. This pipeline stage is generally called a memory stage. The address conversion is performed on the upper address of the virtual address to obtain the upper address of the physical address.
In parallel with this, the fact that the lower addresses of the virtual address and the physical address are the same is used to access the cache memory 1020 by the lower address.
Here, the cache memory 1020 is a small-sized and high-speed memory in which a part of the memory is copied and stored.
The cache memory 1020 stores the upper address of the physical address together with the data, and the upper address of this physical address is read out and compared with whether or not it matches the upper address of the physical address of the conversion result. . If they match, it is determined that the cache memory has been hit, and data reading or writing is executed.

[0006]

As described above, in the conventional microprocessor, it is necessary to perform address addition and address conversion when executing the memory access instruction. Since the virtual address that is the input of the address conversion is obtained as the result of the address addition, the address addition and the address conversion need to be executed sequentially. For this reason,
There is a problem that it takes time to execute the memory access instruction.

In particular, in the typical microprocessor pipeline structure as described with reference to FIG. 10, address addition and address conversion are processed in separate pipeline stages. Therefore, in the conventional microprocessor, in order to process the memory access instruction, one more pipeline stage than the ALU instruction processed in one pipeline stage is required, which is one of the causes for preventing the performance improvement. . In particular, in the case of a load instruction, the read data is often used immediately after, and in this case, there is a problem that the pipeline of the processor stops. The object of the present invention is to solve these problems,
It is an object of the present invention to provide an address conversion device and an address calculation method for a microprocessor, which enables a memory access instruction to be processed at a higher speed.

[0008]

An address translation device for outputting a physical address corresponding to the virtual address as a result of address translation in response to an input of a virtual address, wherein: The physical address PA (VA) corresponding to the virtual address VA
And the physical address PA (VA + 1) corresponding to the virtual address obtained by adding 1 to the virtual address VA,
The physical address PA (VA-1) corresponding to the virtual address obtained by subtracting 1 from the virtual address is also stored together, and at the time of address translation, an input virtual address VA 'input from the outside and a physical address selection For the signal 1 and the physical address selection signal 2, the three physical addresses PA (V
A '), PA (VA' + 1), PA (VA'-1) are selected, and the physical address P selected according to the physical address selection signal 1 and the physical address selection signal 2 is selected.
A (VA '), PA (VA' + 1), PA (VA'-
One of the physical addresses is selected from among 1) and is output as the address conversion result.

A microprocessor address calculation method according to the present invention comprises a register including a base address for reading data from an arbitrary physical address of a storage device or writing data to the arbitrary physical address of the storage device. A displacement from the base address is designated, an address addition for adding the base address and the displacement to obtain a virtual address, and an upper address of the virtual address is input to an address translation device to input the physical address An add-on of a microprocessor, which comprises an address conversion for obtaining the physical address of the storage device by converting it to an upper address and using the lower address of the virtual address as it is as a lower address of the physical address. In the calculation method, the address translation device is used, the number of bits of the lower address of the virtual address is one less than or more than the number of bits of the displacement, and the displacement When the number of bits is smaller than the number of bits of the lower address of the virtual address, the sign extension of the displacement is performed, and the lower address of the base address and the displacement is at the same position and the same number of bits as the lower address of the virtual address. Respectively, the upper address of the base address is defined as an address having the same position and the same number of bits as the upper address of the virtual address, and in the address addition, the lower address of the base address and the lower address of the base address. De Generating the lower address and the carry signal of the virtual address by performing addition with the lower address of the displacement; and, in the address translation, using the upper address of the base address as the input virtual address. The address translation device is supplied with the sign bit of the displacement as the physical address selection signal 1 and the carry signal as the physical address selection signal 2 and is input to the address translation device. An address translation device outputs an upper address of the physical address corresponding to the upper address of the virtual address obtained by adding the base address and the displacement. It is characterized by using.

Further, in the present invention, the address addition and the address conversion are performed in parallel. Further, the address addition and the address conversion are performed in parallel in one pipeline stage of the instruction pipeline in the microprocessor. Alternatively, whether the address addition and the address conversion are performed in parallel in one pipeline stage of the instruction pipeline in the microprocessor, and the cache memory is also accessed in the pipeline stage. Or
The address addition and the address conversion are performed in parallel in one pipeline stage of the instruction pipeline in the microprocessor, and the decoding for access to the cache memory is also performed in the pipeline stage. It is characterized by that.

[0011]

FIG. 8 is an explanatory view for explaining the operation of the present invention. The number of displacement bits is n bits, and the size of the base address is m bits. The positive displacement is shown in FIG. 8a, and the negative displacement is shown in FIG. 8b. As shown in FIG. 8A, when the displacement is positive, in the actual addition operation, the displacement is sign-extended to 0 from the nth bit to the mth bit and added to the base address. Further, as shown in FIG. 8B, when the displacement is negative, in the actual addition operation, the displacement is sign-extended to all 1s from the nth bit to the mth bit and added to the base address. .

Here, the upper address of the virtual address is k
From the 1st bit to the mth bit, the lower address is from the 1st bit to the (k-1) th bit. However, k is an integer equal to or larger than n. Along with this, the upper address of the base address is the same as the upper address of the virtual address, and the address has the same number of bits.
That is, from the kth bit to the nth bit. Also,
The base address and the lower address of the displacement have the same position and the same bit as the lower address of the virtual address, that is, from the first bit to (k
-1) Up to the 1st bit. By determining the size of the upper address and the lower address in this way, the address addition of the upper address is simplified as shown below.

The upper addresses of the virtual address obtained as a result of the address addition will be described in the two cases of FIGS. 8a and 8b. In FIG. 8a, the higher address of the virtual address is generated by adding the higher address of the base address of the virtual address, the sign extension or sign bit of the displacement, and the carry bit resulting from the addition of the lower addresses. Since the sign extension part or the sign bit is all 0, the upper address of the virtual address is the same as the upper address of the base address, or 1 plus the upper address of the base address. Similarly, in FIG. 8b, the higher address of the virtual address is generated by adding the higher address of the base address of the virtual address, the sign extension or sign bit, and the carry bit resulting from the addition of the lower address. Since the sign extension part or sign bit is all 1, and this addition corresponds to the subtraction of 1, the upper address of the virtual address is the same as the upper address of the base address, or 1 is subtracted from the upper address of the base address. It becomes a thing.

As described above, by setting the number of bits of the lower address of the virtual address to be one less than the number of bits of the displacement, the number of bits higher than that of the displacement allows the addition of the higher addresses to be the upper address of the base address + 0.
Alternatively, it is possible to greatly simplify the three types, that is, the upper address of the base address + 1 or the upper address of the base address -1. The present invention utilizes such an action.

[0015]

1 is a block diagram showing an embodiment of an address translation device according to the present invention. 1, the address translation device of the present invention includes a virtual address input terminal 101, a virtual address storage block 110 for storing a virtual address input from the virtual address input terminal 101, a physical address input terminal 102, and a physical address input terminal. 102
Physical address storage block 120 for storing the physical address input from
Physical address buffer 130 that temporarily holds the physical address output from
Selector 140 for selecting one of the physical addresses in
And a physical address selection signal 1 for controlling the selector 140
And physical address selection signal 1 input terminal 103-1 physical address selection signal 2
It comprises an input terminal 103-2 and a translated physical address output terminal 104 which is connected to the selector 140 and outputs the selected physical address as a translated physical address.
The virtual address storage block 110 is further composed of a plurality of virtual address storage fields 115. In FIG. 1, as an example, the virtual address storage field 115 has 5
Although one case is shown as an example, it is generally composed of a larger number of virtual address storage fields 115. One virtual address storage field 115 stores one virtual address. Similarly, the physical address storage block 120 includes a plurality of physical address storage fields 1
25. Physical address storage field 12
5 are provided one by one corresponding to one virtual address storage field 115, and each stores three physical addresses. As shown in FIG. 1, if the virtual address storage field 115-2 stores the virtual address VA1, the corresponding physical address storage field 125-2 corresponds to the virtual address obtained by subtracting 1 from VA1. The physical address, the physical address corresponding to VA1, and the physical address corresponding to the virtual address obtained by adding 1 to VA1 are stored. These physical addresses are assigned to PA (VA1-1) and PA (V
A1) and PA (VA1 + 1).

With such a configuration, the address translation device of the present invention performs address translation as follows. First, the virtual address to be converted is input from the virtual address input terminal 101 as an input virtual address. The input virtual address input is compared with the virtual addresses stored in all virtual address storage fields 115. Three physical addresses are read from the physical address storage field 125 corresponding to the virtual address storage field 115 storing the virtual address that matches the input virtual address to the physical address buffer 130. In response to the physical address selection signals 1 and 2 (103-1, -2), one of the three physical addresses temporarily held in the physical address buffer 130 is selected by the selector 140, and the physical address is selected as the translated physical address. It is output from the address output terminal 104.

FIG. 2 is an explanatory diagram showing a physical address selection method using the physical address selection signal 1 and the physical address selection signal 2. In FIG. 2, it is assumed that VA1 is input as the input virtual address. When the physical address selection signal 1 is 0 and the physical address selection signal 2 is 0, the physical address PA (VA1) is output as the translated physical address. Similarly, when the physical address selection signal 1 is 0 and the physical address selection signal 2 is 1, the physical address PA (V
A1 + 1), when the physical address selection signal 1 is 1, the physical address selection signal 2 is 0, PA (VA-1), when the physical address selection signal 1 is 1, and the physical address selection signal 2 is 1, PA (VA1) Is output.

FIG. 3 is an explanatory view showing a first embodiment of the address calculation method of the microprocessor using the address conversion device according to the embodiment of FIG. In FIG.
As an example, the number of bits of the base address 320 is 64 bits, and the number of bits of the displacement 330 is 16 bits. Further, as an example, the lower address of the virtual address is 15 bits, and the upper address is 49 bits. Therefore, the number of bits of the lower address 325-2 of the base address 320 and the lower address 335-2 of the displacement is 15 bits, and the base address 3
The number of bits of the 20 high-order addresses 325-1 is 49 bits. The number of bits of the lower address 325-2 of the base address is one less than the number of bits of the displacement 330.

Using the base address 320 and the displacement 330, the upper address 325-1 of the base address 320 is first input to the address translation device 340 as an input virtual address. Further, the lower address 325-2 of the base address 320 and the lower address 335-2 of the displacement 330 are added by the adder 310. The addition result is output from the lower physical address output terminal 302 as a lower address of the physical address. The carry signal output 315 of the adder 310 is input to the address conversion device 340 as the physical address selection signal 2. The lower address 335-2 of the displacement 330 is the displacement 330 minus the sign bit 335-1. The sign bit 335-1 of the displacement 330 is input to the address conversion device 340 as the physical address selection signal 1. The translated physical address 341 output from the address translation device 340 is output from the upper physical address output terminal 301 as an upper address of the physical address. By these physical address selection signals 1 and 2, the positive and negative of the displacement 330 and the base address 320
The correct physical address according to the carry signal generated by the addition of the lower addresses of the displacement 330 and the displacement 330 is selected and output by the address conversion device 340.

FIG. 4 is an explanatory diagram showing a second embodiment of the address calculation method of the microprocessor using the address conversion device according to the embodiment of FIG. In FIG.
As an example, the number of bits of the base address 420 is 64 bits, and the number of bits of the displacement 430 is 16 bits. As an example, the lower address of the virtual address has 18 bits, and the upper address has 46 bits. Therefore, the lower address 425-2 of the base address 420 and the lower address 435-2 of the displacement have 18 bits, and the upper address 425-1 of the base address 420 has 46 bits. Displacement 4
Since the number of bits of 30 is smaller than the number of bits of the lower address of the virtual address, the displacement 430 is sign-extended according to the value of the sign bit 435-1.
Lower address 435-2 of displacement 430
Also includes a sign extension 440.

Using the base address 420 and the displacement 430, the upper address 425-1 of the base address 420 is input to the virtual address translation device 440 as an input virtual address. Also,
The lower address 425-2 of the base address 420 and the lower address 435-2 of the displacement 430 are added by the adder 410. The addition result is used as the lower address of the physical address, and the lower physical address output terminal 402
Output from. Carry signal output 415 of adder 410
Is an address translation device 4 as a physical address selection signal 2.
40 is input. The sign bit 435-1 of the displacement 430 is input to the address translation device 440 as the physical address selection signal 1. The translated physical address output from the address translation device 440 is output to the upper physical address output terminal 40 as an upper address of the physical address.
It is output from 1.

In the embodiment of the method of calculating the address of the microprocessor according to the present invention shown in FIGS. 3 and 4, the address addition is executed only for the lower address. Further, the address conversion is executed only for the upper address. A carry signal is generated by the address addition of the lower address, and the address conversion device 3 is used as the physical address selection signal 2.
40 or 440, which is required by the address translator 340 or 440.
It is used to select one physical address from the above three physical addresses after three physical addresses corresponding to the input virtual address are selected. Since most of the time required for address translation is spent for selecting the physical address corresponding to the virtual address, it is sufficient if the carry signal is input at the time when most of the address translation is completed. Therefore, in the first and second embodiments of the address calculating method according to the present invention shown in FIGS. 3 and 4, the address calculation and the address conversion can be executed in parallel.

FIG. 5 is a block diagram for explaining a pipeline structure of a microprocessor which realizes a third embodiment of the address calculating method of the microprocessor according to the present invention. In the embodiment of FIG. 5, an adder 510 that performs address addition for lower addresses and an address translator 520 that performs address translation for higher addresses.
However, the feature is that they operate in parallel in one pipeline stage of the instruction pipeline of the microprocessor. The operation of this embodiment will be described below.

In FIG. 5, base address input terminal 5
The base address 551 is input from 01, and the displacement 5 is input from the displacement input terminal 502.
52 is input. The lower address 511 of the base address 551 and the lower address 512 of the displacement 552 are added by the adder 510 to obtain the lower physical address 5
It is output from the lower physical address output terminal 504 as 54. The upper address 521 of the base address 551
As the input virtual address, the displacement 55
The sign bit 523-1 of 2 is used as the physical address selection signal 1, the carry signal 523-2 of the adder 510 is used as the physical address selection signal 2, and the address converter 520 is used.
Entered in. The translated physical address output from the address translator 520 is output from the upper physical address output terminal 503 as the upper physical address 553.

FIG. 6 is a block diagram for explaining a pipeline configuration of a microprocessor which realizes a fourth embodiment of the address calculating method of the microprocessor according to the present invention. In the embodiment of FIG. 6, an adder 610 that performs address addition for lower addresses and an address translator 620 that performs address translation for higher addresses operate in parallel in one pipeline stage of the microprocessor's instruction pipeline. In addition, the feature is that the cache memory 630 is also accessed in the same pipeline stage. The operation of this embodiment will be described below by taking a load instruction as an example.

In FIG. 6, the base address input terminal 6
The base address 661 is inputted from 01, and the displacement 6 is inputted from the displacement input terminal 602.
62 is input. The lower address 611 of the base address 661 and the lower address 612 of the displacement 652 are added by the adder 610 to obtain the lower physical address 6
It is output as 13. The upper address 621 of the base address 661 is used as an input virtual address, the sign bit 623-1 of the displacement 662 is used as the physical address selection signal 1, and the carry signal 62 of the adder 610 is used.
3-2 is input to the address converter 620 as the physical address selection signal 2. Address converter 620
The converted physical address that is the output of
It is output as 4. The lower physical address 613 is input to the decoder 631 of the cache memory 630, and the data and the upper address corresponding to the lower physical address 613 are read from the data unit 632 and the tag unit 633, respectively. The read higher physical address is compared with the converted physical address 624 by the comparator 635, and if they match,
The data read from the data section 632 is the selector 63.
The read data 665 is output from the read data output terminal 605 as read data 665.

In the embodiment of the address calculation method of FIG. 6, the address calculation by the adder 610 and the access to the cache memory 630 can be executed in parallel with the address conversion in the address converter 620.

FIG. 7 is a block diagram for explaining a pipeline structure of a microprocessor for realizing a fifth embodiment of the microprocessor address calculating method according to the present invention. In the embodiment of FIG. 7, an adder 710 that performs address addition for lower addresses and an address translator 720 that performs address conversion for higher addresses are arranged in parallel in one pipeline stage of the instruction pipeline of the microprocessor. It is characterized in that it operates, and further, the decoder 731 for accessing the cache memory also operates in the same pipeline stage.
The operation of this embodiment will be described below.

In FIG. 7, base address force terminal 70
1, the base address 771 is input, and the displacement input terminal 702 inputs the displacement 77.
2 is input. Lower address 711 of base address 771 and lower address 7 of displacement 752
12 is added by the adder 710 to obtain the lower physical address 71
It is output as 3. The upper address 721 of the base address 771 is used as an input virtual address, the sign bit 723-1 of the displacement 772 is used as the physical address selection signal 1, and the carry signal 723 of the adder 710 is used.
-2 is input to the address converter 720 as the physical address selection signal 2. The translated physical address output from the address translator 720 is the upper physical address 724.
Is output from the higher physical address output terminal 703. The lower physical address 713 is input to the decoder 731 of the cache memory, and the decode signal 706 is output.

[0030]

According to the address calculation method in the microprocessor of the prior art, it is necessary to add the addresses to all the bits of the virtual address. By the address translation device and the address calculation method using the same according to the present invention, the number of bits required for address addition is reduced to the number of bits designated as the lower address of the virtual address. Since the addition process takes more time as the number of bits increases, it is possible to shorten the address addition time. Also, the hardware of the adder can be downsized.

Further, in the address calculating method of the present invention, it is possible to process the address conversion for the upper address and the address addition for the lower address in parallel. This makes it possible to shorten the address calculation time.

Further, in the address calculating method of the present invention, the address conversion and the address addition are performed in parallel in one pipeline stage so that the address conversion is performed in the pipeline stage before accessing the cache memory. It is possible to take the method of closing.
In the conventional address calculation method, since the address conversion and the access to the cache memory are performed in parallel, in the case of the direct map cache memory that accesses by the physical address, there is a problem that a cache memory larger than the page size cannot be realized. It was Such a problem can be solved by the above pipeline construction method based on the address calculation method of the present invention.

Further, in the address calculating method of the present invention, in addition to performing address conversion and address addition in parallel in one pipeline stage, the address to the cache memory is also performed in the same pipeline stage. It is also possible to take a method. This allows
Address calculation and cache memory access can be combined into one pipeline stage. In the conventional technique, the address calculation and the access to the cache memory are executed in different pipeline stages. Therefore, compared to the ALU instruction and the like, there is a problem that it takes an extra time to execute the memory access instruction for one cycle or more. This is because the addition of all the bits of the virtual address takes time for one stage of the pipeline stage to add the address. Such a problem can be solved by the above pipeline construction method based on the address calculation method of the present invention.

Finally, in the address calculation method of the present invention, in addition to performing address conversion and address addition in parallel in one pipeline stage, decoding for accessing the cache memory is performed in the same pipeline stage. It is also possible to do it in-house. In the prior art, even the decoding is performed in the pipeline stage for accessing the cache memory.
Therefore, a time close to half of the processing time of this pipeline stage was spent for decoding. By the above pipeline configuration method based on the address calculation method of the present invention, the execution time of the pipeline stage can be shortened if the cache memory size is the same, and if the pipeline stage execution time is the same, the cache is executed. There is an advantage that the memory size can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an address translation device according to the present invention.

FIG. 2 is an explanatory diagram explaining an operation of an embodiment of the address translation device of FIG.

FIG. 3 is an explanatory diagram showing a first embodiment of a method of calculating an address of a microprocessor according to the present invention.

FIG. 4 is an explanatory diagram showing a second embodiment of the microprocessor address calculation method according to the present invention.

FIG. 5 is a block diagram showing a pipeline configuration of a microprocessor that implements a third embodiment of the microprocessor address calculation method according to the present invention.

FIG. 6 is a block diagram showing a pipeline configuration of a microprocessor for realizing a fourth embodiment of the microprocessor address calculating method according to the present invention.

FIG. 7 is a block diagram showing a pipeline configuration of a microprocessor that implements a fifth embodiment of the microprocessor address calculation method according to the present invention.

FIG. 8 is an explanatory diagram showing the operation of the present invention.

FIG. 9 is an explanatory diagram showing an outline of a method of calculating an address of a memory access instruction according to a conventional technique.

FIG. 10 is a block diagram showing a pipeline configuration of a microprocessor for explaining a processing procedure of an address calculation method in a conventional technique.

[Explanation of symbols]

 101 virtual address input terminal 102 physical address input terminal 103-1 physical address selection signal 1 input terminal 103-2 physical address selection signal 2 input terminal 104 translation physical address output terminal 110 virtual address storage block 115 virtual address storage field 120 physical address storage Block 125 physical address storage field 130 physical address buffer 140 selector

Claims (6)

[Claims] 1. An address translator that outputs a physical address corresponding to the virtual address as a result of address translation in response to input of a virtual address, wherein the virtual address VA corresponds to the arbitrary virtual address VA. The physical address PA (VA), the physical address PA (VA + 1) corresponding to the virtual address obtained by adding 1 to the virtual address VA, and the physical address corresponding to the virtual address obtained by subtracting 1 from the virtual address. PA (VA-1) is also stored together, and at the time of address conversion, the input virtual address VA is input with respect to the input virtual address VA ′ and the physical address selection signal 1 and the physical address selection signal 2 input from the outside. 'The three physical addresses PA (V
A '), PA (VA' + 1), PA (VA'-1) are selected, and the physical address P selected according to the physical address selection signal 1 and the physical address selection signal 2 is selected.
A (VA '), PA (VA' + 1), PA (VA'-
The address translation device, further selecting one of the physical addresses from 1) and outputting it as the address translation result. 2. A register including a base address and a displacement from the base address are used when reading data from an arbitrary physical address of the storage device or writing data to the arbitrary physical address of the storage device. Address addition for designating and adding the base address and the displacement to obtain a virtual address, inputting an upper address of the virtual address to an address translation device and converting the upper address of the physical address to the virtual address The address calculation method for a microprocessor, comprising: address conversion for obtaining the physical address of the storage device by directly using the lower address of the physical address as the lower address of the physical address. Address of Using a translation device, the number of bits of the lower address of the virtual address is one less than or more than the number of bits of the displacement, and the number of bits of the displacement of the virtual address If the number of bits is smaller than the number of bits of the lower address, the sign extension of the displacement is performed, and the lower address of the base address and the displacement is defined as an address having the same position and the same number of bits as the lower address of the virtual address. , An upper address of the base address is defined as an address having the same position and the same number of bits as the upper address of the virtual address, and in the address addition, the lower address of the base address and the lower address of the displacement. To generate a lower address and a carry signal of the virtual address, and in the address translation, the upper address of the base address is input to the address translation device as the input virtual address. Then, the sign bit of the displacement is used as the physical address selection signal 1 and the carry signal is input as the physical address selection signal 2 to the address translation device, and the address translation device responds to these inputs, An address calculation method for a microprocessor, comprising: outputting an upper address of the physical address corresponding to the upper address of the virtual address obtained by adding the base address and the displacement. 3. The address calculation method for a microprocessor according to claim 2, wherein the address addition and the address conversion are performed in parallel. 4. The method of calculating an address of a microprocessor according to claim 3, wherein the address addition and the address conversion are performed in parallel in one pipeline stage of an instruction pipeline in the microprocessor. . 5. The address addition and the address conversion are performed in parallel in one pipeline stage of an instruction pipeline in a microprocessor, and further,
4. The method of calculating a microprocessor address according to claim 3, wherein the cache memory is also accessed in the pipeline stage. 6. The address addition and the address conversion are performed in parallel in one pipeline stage of an instruction pipeline in a microprocessor, and further,
4. The address calculation method for a microprocessor according to claim 3, wherein decoding for accessing the cache memory is also performed in the pipeline stage.