JPS60129839A - Information processor - Google Patents

Abstract

PURPOSE:To cause no execution stop of a following instruction, and to improve a pipeline control by constituting so that a processing of the following instruction which is stopped at the time of confliction of a register can be started by using a forecasting outputted by a forecasting device. CONSTITUTION:The second operand data of a precedent instruction is stored in advance instead of an operation result of the precedent instruction in an associative storage device 320. When the precedent instruction is executed, the associative storage device 320 outputs the second operand data by the previous execution to a signal line 538 by an associative key. An operand code of the precedent instruction is inputted to an arithmetic logical circuit ALU360 through a signal line 604, and a register value of the precedent instruction is selected by a selector to which a field of its register has been applied, and inputted to the ALU360 through a signal line 606. As a result, a forecasting value is outputted to a signal line 600, and the following instruction is executed without an idle time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing device, and particularly to speeding up an information processing device using pipeline control.

[Background of the invention]

In a pipeline-controlled information processing device, the entire instruction processing is divided into a number of sets of partial processing, and an independent processing device is provided for each partial processing. First, a first instruction is processed by a processing device that performs a first partial process.

When the processing is completed and the processing moves to the processing device that performs the second partial processing, the processing device that performs the first partial processing starts processing the second instruction. When the first instruction is transferred to the processing device that performs the third partial processing, the second instruction is processed by the processing device that performs the second partial processing, and the third instruction is processed by the first partial processing device. In this way, execution of instructions subsequent to the first instruction is started before the entire processing of the first instruction is completed, so that high instruction processing performance can be achieved in an information processing device using pipeline control.

However, if an instruction (hereinafter referred to as the preceding instruction) that precedes a certain instruction (hereinafter referred to as the subsequent instruction) modifies a certain register, and the subsequent instruction is an instruction that references that register (register conflict occurs). It's called a state.

), instruction processing does not proceed as described above. That is,
Until the preceding instruction writes the operation result to the register or until the preceding instruction generates the operation result, the entire processing of the subsequent instruction 5 or at least the partial processing that refers to the register must be stopped. Suspension of execution of subsequent instructions due to such a registration conflict is a major impediment to performance improvement in pipeline-controlled information processing devices.

[Purpose of the invention]

An object of the present invention is to provide a pipeline-controlled information processing device that eliminates the suspension of execution of subsequent instructions when a register conflict occurs and has high instruction processing performance.

[Summary of the invention]

In the present invention, the instruction address or a part thereof of the preceding instruction causing a register conflict with the succeeding instruction, the instruction address or a part thereof of the instruction before the preceding instruction, and the preceding instruction are read in advance. the prefetch address or part thereof when prefetching an instruction before the preceding instruction; the contents of a register referred to by the preceding instruction, or a part thereof; and the preceding instruction. a device for predicting the operation result of the preceding instruction by using the entire word or a part thereof or any combination of each part as an associative key; a device that detects whether a predicted value of an operation result of an instruction has been output, and when detected, uses the predicted value to start the stopped processing of the subsequent instruction; An information processing device is provided that has a device that compares whether the operation result to be written is equal or not, and when the comparison result is a mismatch, causes the preceding instruction to re-execute the subsequent instruction using the operation result written to the register. suggest.

Thereby, the processing of a subsequent instruction that is stopped when a register conflict occurs can be started using the prediction output from the prediction device, so that the above object can be achieved.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, the instruction format used in this embodiment will be explained using FIG. 1A. In this instruction format, each instruction word has a length of 4 bytes. The first byte represents the opcode (0P). The upper four bits of the second and third bytes represent three register designation fields (R1, X2.B3). The lower four bits of the third byte and the fourth byte represent displacement (D2).

In this instruction format, each register designation field is 4 bits each and each designates one of the 15 registers.

The meaning of this instruction is that the operand address is the sum of the contents of the general-purpose register indicated by the The operation indicated by the operation code 0P is performed on the contents of the general-purpose register indicated by the R1 field (called the first operand) and stored in the general-purpose register indicated by the R1 field.

Note that this instruction format is IBM System/3
70 from the instruction format, and for more details, see “IBM System/370 Pr1nci.
Please refer to ``Pres of Pera-tion''.

FIG. 1B is a mnemonic representation of the command shown in FIG. 1A.

FIG. 2 is an example of an instruction sequence causing a registration conflict. The preceding instruction (■) is an Add instruction, which means that the contents of the address obtained by adding the contents of register 1, contents of register 2, and displacement 100 are added to the contents of register 5, and the result is stored in register 5. . Subsequent instruction (■)
is a Sub'5t-ract instruction, which means to subtract the contents of register 1 and the contents of the address obtained by adding the contents of register and displacement 150 from the contents of register 8 and store them in register 8.

Since the preceding instruction writes the operation result to register 5, and the subsequent instruction uses the contents of register 5, a register conflict occurs.

Next, an overview of the overall configuration of the embodiment will be explained using FIGS. 3A and 3B. When FIG. 3A and FIG. 3B are combined,
This is an overall configuration diagram of the embodiment. In this embodiment, the calculation result of the previous execution of the preceding instruction is used as the predicted value of the calculation result of the preceding instruction.

First, 304 is an instruction storage device, and 326 is an operand storage device. The instruction storage device 304 and the operand storage device are addressed by 24-bit addresses in units of bytes.

100 is a prefetch instruction register. Prefetching the command is
This is always performed in units of four instruction words starting from the four instruction word boundary on the instruction storage device. Therefore, the look-ahead instruction register (I
FA) 100 stores the upper 20 bits (bits 0-19) of the 24-pill address.

102 is a delay register of the prefetch instruction register.

LO4, 106, 108, l'lo are instruction buffers IBO, IBM, IB2. IB3, and the four instruction words read ahead from the instruction storage device 304 are stored in this order.

112 is an instruction register, and 114 is an instruction counter. One instruction word consists of 4 points from the instruction word boundary on the instruction storage device.
Always placed in the byte. Therefore, the upper 22 bits (bits 0-21) of the 24-bit address are stored in the instruction counter. The value of the instruction counter 114 is
This is the instruction address of the instruction word in the instruction register 112 at that time.

Hard It is Isle.

324 is an address adder, and the content of the register indicated by the X2 field of the instruction word, that is, the X2 register value, and the content of the register indicated by the 82 field, that is,
Add B2 register value and displacement D2. The addition result is stored in operand address register 120.

122 is an operand data register, and 330 is an A
It is LU.

124.1.30, 132, 134, and 136 are the delay register of the instruction register 122 and the instruction counter 11, respectively.
4 delay register, X2 register value delay register, B
It is a delay register for the delay register value of 2 registers and a prefetch instruction address, and an operand address register 1.
When the operand address is stored in 20, the instruction register value, instruction counter value, X2 register value,
The B2 register value and the prefetch instruction address at the time of prefetching the instruction are stored.

T')G, +"lR-+41'l 1A2- 144 are registers 124, 138, 140, 142°1, respectively
44 delay registers, and when operand data is stored in the operand data register 122, the instruction register value, instruction counter value, X2 register value,
The B2 register value and the prefetch instruction address at the time of prefetching the instruction are stored in each Jl.

320 is an associative memory device used as a predictive storage device, and 322 is a register conflict detection device.

154 is a register that stores the predetermined value of the operation result output by the prediction device, and 332 is a comparator that compares whether the predicted value of the operation result output by the prediction device is equal to the operation result determined by the instruction. be.

Next, the overall operation in the case where there is no register conflict will be described using the overall configuration diagrams in FIGS. 3A and 3B and the timing charts 1 to 1 in FIG. 5.

As shown in FIG. 5, it is assumed that the prefetch address for prefetching the first to fourth instructions is stored in the prefetch address register from time To. Further, it is assumed that the instruction register 112 and the instruction counter 114 store the instruction word and instruction address of the instruction before the first instruction, that is, the 0th instruction before time T2. Look-ahead address register 100
The address of is sent to the instruction storage device 304 via the signal line 500.
The four command words starting from that address are output to the signal line 506, and the four command words from the first command word to the fourth command word
The instruction word is sent to the buffer 104°106.108 at time T1.
110.

The address incrementer 302 is a look-ahead address register 1O.
An address of 0 is input, and an address incremented by 4 instruction words is output to the signal line 502. The signal on the signal line 586, which is the selection signal of the selector 300, is normally “
"right selection signal" (the only time it takes a value other than "right selection signal" is as explained below), and at this time, the signal on signal line 502 passes through selector 300 and is output to signal line 506. and stored in the prefetch address register 100. The stored time is time T4, which is four cycles after time TO. These four instruction words are stored in the instruction buffer 104.10'6°108.110 until time T5 when the next four instruction words are stored. Since the prefetch address register 100 is normally increased by four instruction words in this way, the instruction buffers 104, 106, 108 . ．． Subsequent instructions are sequentially read ahead and stored in the memory 110 in units of four instructions.

Before time T2, the instruction counter 114 has the 0th
The instruction address of the instruction was stored.

The value of instruction counter 114 is applied to address incrementer 310 via signal line 530 and is incremented by one instruction word.
This is the instruction address of the first instruction. The increased value is input to selector 3O8 via signal line 520. As mentioned above, the selection signal 586 of the selector 308 is usually the "right selection signal", and at this time, the value of the signal line 520 is the same as that of the selector 3.
08 to the signal line 518. Signal line 518
The value of is stored in the instruction counter 114. The value is also applied to selector 306. The selector 306 selects the 22-bit address value Q+-/7'I on the signal line 518.
w: tsu l/-,,, L b w y z h, +t
n? , Q +, f Ifr @ #,! Data on Z508 is output to signal line 516, and if it is 1, data on signal line 510 is output to signal line 516. If it is 2, the data on the signal line 512 is output to the signal 516, and if it is 3, the data on the signal line 514 is output to the signal line 516.
Output to.

As a result, the contents of the instruction buffer next to the instruction buffer set at the time before the instruction register are selected by the selector 306 and stored in the instruction register 117. Time T2
In the step, the first instruction word from the instruction buffer IBO 104 is stored in the instruction register 112, and at the same time, the instruction address of the first instruction is stored in the instruction counter 114.

In addition, the I FAD register 102 contains the following information at time T2, which is two cycles behind the prefetch instruction address register IFA100.
The value of the prefetch instruction address register is stored.

16 to the selectors 312 and 314 via the signal line 532.
The values of a register file 118 consisting of registers are applied. Furthermore, four bits of the X2 field of the first instruction in the instruction register 112 are applied to the selector 312 via a signal line 524. This causes the selector 312 to
The value of the register indicated by field 2 is output to the signal line 534. The selector 314 is further applied with 4 pins 1- of the B2 field of the first instruction in the instruction register 112 via a signal line 526. The selector 314 thereby sends the value of the register indicated by the B2 field to the signal line 536.
Output to. Normally, the "2 selection signal" is applied to the signal lines 592 and 590 (a value other than the "upper selection signal" is applied only in the case described below), and at this time, the signal line 534 The value of is passed through the selector 316 to the signal line 5.
40, and the value of signal line 536 is outputted to signal line 542 via selector 318.

In this way, the contents of the register indicated by the X2 field of the first instruction are input to the address adder via the signal line 540, and the contents of the register indicated by the B2 field of the first instruction are input via the signal line 542.
The contents of the register indicated by the field are input. Furthermore, the first
The command displacement D2 is input. The address adder is 3 above.
The operand address of the first instruction, which is the result of adding the two input values, is output to the signal line 548, and is stored in the operand address register 120 at time T3.

Also, at the same time, the first command word of the IRIR1 register 124 is stored via the signal line 522, and the ICI register 130
The first instruction address is stored in the GRXI register 132 via the signal line 530, the X2 register value of the first instruction is stored in the GRXI register 132 via the signal line 540, and the B2 register value of the first instruction is stored in the GRB 11. It is stored via the signal line 542, and the IFA register 136 stores the prefetch instruction address when the first instruction is prefetched.

The operand address of the first instruction in the operand address register 120 is applied to the operand storage device 326 via a signal line 550, and the operand data of the first instruction at the location indicated by the address is outputted to the signal line 552. Ru.

At time T4, the operand data of this first instruction is stored in the operand data register 122).

At the same time, the IRIR1 register first instruction word is stored in the jR2 register 126 via the signal line 562, and the IC
'2 register 138 is connected to ICI via signal line 572.
The instruction address of the first instruction is stored from the register 130, and the GRX2R1 register 14O signal line 570 is stored.
The X2 register value of the first instruction is stored from the RXI register 132; the B2 register value of the GRB]R1 register 1341 instruction is stored via the GRB2R1 register 142 signal line 568; The prefetch instruction address at which the first instruction word was prefetched from the IFAI register 136 is stored.

ALU 330 has three input signal lines. signal line 55
4, the first
Operand data for the instruction is input. 1 from the signal line 594. The opcode of the first instruction in the R,2 register 126 is input. A register file 11 consisting of 16 registers is connected to the selector 328 via a signal line 532.
A value of 8 is applied, and the R11 field of the first instruction is also applied via signal line 558. Thereby, the selector 328 applies the value of the register indicated by the R1 field, that is, the R1 register value, to the signal line 560, which is input to the ALU 330. The ALU uses the input data from the signal line 560 as first operand data and the input data from the signal line 554 as second operand data, performs an operation on both of them using the opcode shown on the signal line 594, and outputs the result of the operation as a signal. output on line 556.

The calculation result of the first instruction is applied to the register file 118 via a signal line 556, and the I/O signal is applied via a signal line 558.
The R1 field of the first instruction in R2 register 126 is applied. At time T5, the operation result of the first instruction is stored in the register indicated by the R1 field, that is, R1.
written to a register.

With the above steps, the processing of the first instruction is completed.

In the processing of the second instruction, first, at time T3, the second instruction word is stored in the instruction register 112, and the instruction address of the second instruction is stored in the instruction counter IC. Thereafter, the processing proceeds in the same way as the first instruction.

The processing of the third and subsequent commands is performed at a time one cycle behind the processing of the previous command. Proceed as per the second command.

However, since the prefetching of instructions is in units of four instruction words, the prefetching instruction register 100. Instruction buffer 104°106.
108,110. Storage into the IFAD register 1O2 is performed once every four cycles.

As mentioned above, if there is no register conflict, 1
Instruction processing progresses in each cycle.

Next, we will move on to an explanation of the overall operation when there is a register conflict, but before that, we will explain the content addressable memory device 3 using FIG.
Explain 20.

The content addressable memory device in this embodiment has a storage capacity of 10 words.

Each word is divided into an IC storage section ICP346 and an IR storage section IR.
P348 and X2 register value storage unit GRXP350 and B2
It consists of a register value storage unit GRBP352, a prefetch instruction address storage unit IFAP354, and a prediction data and prediction data storage unit PDP356.

Applying data to signal lines 530, 522, 540, 542, and 500 causes the content addressable memory to search. signal line 5
30, 522', 540, 542. Data on 500 and IC storage unit ICP346. IR storage unit IRP348. X
2 register value storage unit GRXP350. B2 register value storage unit GRBP352, prefetch instruction address storage unit IFA
When there is a word in which all the data in P354 match, the match detector 344 outputs "1" and outputs HITL.
The register 156 is set to “1” and the data in the prediction data storage unit FDP356 of that word is transferred to the PD register 158.
Store in. When there is no matching word, match detector 3
44 outputs [0] and sets the HITL register 156 to "0".
”.

On the other hand, “1” is placed on the signal line 584 or “0” is placed on the signal line 586.
is applied, the associative memory device outputs line 45 580.
, 564.5'78, 576.574°556 are stored in the IC storage unit ICP346 and the IR storage unit IR, respectively.
P348. X2 register value storage unit GRXP350. B2
Register value storage unit GRBP352. Prefetch instruction address storage unit IFAP354. Prediction data storage unit FDP356
Register the word to be used as data. At that time, the IC storage unit ICP346. IR storage unit IRP34B, X2 register value storage unit GRXP350. B2 register value storage unit GRB
P352. When a word in which all the data in the prefetch instruction address storage unit 1FAP 354 match has already been stored, the word is overwritten on top of that word. If no matching word is stored, a new word is created and registered.

This concludes the explanation of the associative memory device.

Next, the operation when there is a register conflict will be explained. Consider the two instructions in Figure 2 as instructions with register conflicts, with the Add instruction as the first instruction and 5ubs as the first instruction.
It is assumed that the tract instruction is the second instruction. The third and subsequent instructions are any instructions that do not cause register conflicts 1 to 1 with these instructions.

In the present invention, an associative memory device is used to predict the operation result of the preceding instruction (the first instruction in the example considered below) that has caused a register conflict. Therefore, when a preceding instruction is executed, whether prediction is possible or not depends on whether or not the associative memory device has information about the previous execution.

First, a case will be described in which the associative memory device contains information from previous executions, that is, calculation results. FIG. 6 is used as a timing chart.

Most of the instruction prefetching from the first instruction to the fourth instruction and the processing of the first instruction are the same as those in the case where there is no register conflict as described above. That is, in the timing chart of FIG. 6, IFA for the first to fourth instructions, IBO to 3IFAD, and IR/IR for the first instruction.
IC, OA/IRI/IC1/GRX1/GRB1/'
IFAI.

○D/IR2/IC2/GRX2/C; RB2/IFA
2. The timing of GR is the same as in FIG.

The other parts will be explained below.

First, from time TO, the prefetch instruction address register 100
The prefetch instruction address stored in the signal line 500
The prefetch instruction address storage unit IF of the associative memory device via
It is applied to AP354.

Also, at time T2, the instruction word of the first instruction, the instruction address X2 register value, and the B2 register value are respectively transferred to the signal line 5.
22, 530, 540, and 542 respectively to the IR storage section 348. X2
Register value storage unit 350° B2 register value storage unit 352
is applied to

The associative memory device is connected to the signal line 530. '522゜540
．． Search using 542,500 data.

Now, we are considering a case where the associative memory has information from the previous execution, so at time T3, the PDL register 15
8 stores the child ai value of the operation result of the first instruction, and H
“1” is stored in the ITL register 156. Furthermore,
This “1” is applied to signal line 546.

At time T3, the instruction word of the A'dd instruction, which is the first instruction, is stored in the IRI register 124, and the instruction word of the 5ubstract instruction, which is the second instruction, is stored in the instruction register 112.

Therefore, the R1 field "5" of the first instruction is applied to the signal line 582, and the X2 field "5" of the second instruction is applied to the signal line 524.

Since it is assumed that there is no register confrifter for instructions other than the first and second instructions, the signal lines 558 and 526 have [5
” is applied.

Therefore, the output of the minus number comparison circuit 160 becomes "1", and the outputs of the other coincidence comparison circuits 162, 164, and 166 become "1".
0". Therefore, the output signal line 593 of the OR circuit 168, the output signal line 596 of the OR circuit 182, and the AND circuit 17
The output signal line 172 of No. 2 becomes "1". Also, the output signal line 591 of the OR circuit and the output signal line 5 of the AND circuit 174
90. The output signal line of the AND circuit 180 becomes "0".

The signal line 596 is a set signal for the IC8V register 158, and since this signal line is rlJ, the instruction address of the second instruction is stored in the IC3V register 116 at time T4, and the operation result of the first instruction is stored in the PDSV register 154. Predicted values are stored.

29, the selector 316 applies the predicted value of the operation result of the first instruction on the signal line 538 to the address adder 324 via the signal line 540;
The B2 register value of the second instruction above is applied to address adder 324 via signal line 542. From signal line 528, the displacement of the second instruction is applied to the address adder. As a result, at time T4, the operand address of the second instruction is stored in the operand address register 20.

Additionally, the LRI register 124. ICI register 130,
GRXI register 132. GRI3 Lujistar 134. I
The same data as in the operation when there is no register conflict 1- is stored in the FAI register 136 at time T4.

The subsequent operation of the second instruction proceeds in the same way as in the case where there is no register conflict.

The calculation of the first instruction is being performed in the ALU 330 from time T4, and the calculation result is applied to the comparator 332 via the signal line 556 between times T4 and T5. Comparator 33
The predicted value of the operation result of the first instruction stored in the PDSV register is applied to the other input of No. 2.

The following operation is divided into two types depending on whether the calculation result in the ALU 330 matches the predicted value or not. First, the case where they match will be explained. In this case, “1” is applied on signal line 586. This "1" is input to selectors 300 and 308. At this time, the selector 300 outputs the data on the signal line 502 to the signal line 506, and the selector 308 outputs the data on the signal line 502 to the signal line 506.
Data of 0 is output to the signal line 518. This is the same behavior as if there were no register conflicts.

The subsequent operations proceed in the same way as in that case.

A case where the calculation result in the ALU 330 does not match the predicted value will be described next. Although FIG. 6 has been used as a timing chart in the above explanation, FIG. 7 will be used in the following explanation. In this case, “0” is applied to the signal line 586. This [0] is input to selectors 300 and 308. At this time, the selector 300 outputs the data on the signal line 504 to the signal line 506, and the selector 308 outputs the data on the signal line 504.
data is output to the signal line 518. As a result, at time T5, the upper 20 bits of the instruction address of the second instruction stored in the IC3V register 116 are stored in the prefetch instruction address register 100. This value is the same as the prefetch addresses for the first to fourth instructions. As a result, lookahead is executed, and at time T6, the first to fourth instructions are transferred to the instruction buffers 104, 106, 108, 1.
10. Since the instruction address of the second instruction is applied to the signal line 518, the second instruction on the instruction register 106 is stored in the instruction register 112 at time T7. The first instruction, which had a register conflict with the second instruction, has already transferred the operation result to R1 at time 5.
It is written to the register indicated by the field. Therefore, at time 1-7, there is no register conflict 1- between the first and second instructions, and the second instruction proceeds in the same manner as described in the case where there is no register conflict 1-.

Additionally, a "0" on signal line 586 is applied to the content addressable memory. As a result, the IC storage section 346 of the associative memory device.
IR storage section 348. X2 register value storage section 350. B2
Register value storage unit 352° Prefetch instruction address storage unit 3
54. Each prediction data storage unit 356 has a signal line 580.
the instruction address of the first instruction above, the first instruction word on signal line 564;

X2 register value of the first instruction on signal line 578, signal line 5
B2 register value of the first instruction on signal line 576, prefetch instruction address when prefetching the first instruction on signal line 574, signal line 55
The word that is the operation result of the first instruction on 6 is registered at time T5.

This concludes the explanation of the case where the calculation result in the ALU 330 does not match the predicted value.

Moreover, this concludes the description of the case where the associative memory has information from a previous run.

Next, a case where there is no information about previous execution in the associative memory will be described. FIG. 8 is used as a timing chart.

The prefetching of the instructions from the first to the fourth instructions and most of the processing of the first instruction are the same as the operations described above when there is no register conflict. That is, in the timing chart 1 of FIG. 8, IFA for the first to fourth instructions, TBO to ■FAD, and IR/
IC, OA/IR1/ICI/GRXI/GRB 1/
I FΔ”.

○D/IR2/IC2/GRX2/GRB2/IFA2
．． The timing of GR is the same as in FIG. The other parts will be explained below.

First, from time TO, the prefetch instruction address register 100
The prefetch instruction address stored in the prefetch instruction address is sent to the prefetch instruction address storage unit 1FA of the associative memory device via the signal line 500.
P354 is applied.

Furthermore, at time T2, the instruction word of the [th] instruction, the instruction address X2 register value, and the B2 register value are respectively
22, 530, 540, 542, respectively, through the 1R storage section 348 and the IC storage section 346. X2 register value storage section 350° is applied to B2 register value storage section 352.

The associative memory device is connected to the signal lines 530, 522.540.5.
Search using 42,500 pieces of data. We are currently considering a case where the year associative memory does not have information from previous executions, so
At time T3, the HIT'L register 156 is set to "0".
is stored. Furthermore, this “0” signal line 546 is applied.

At time T3, the instruction word of the Add instruction, which is the first instruction, is stored in the IR register 124, and the instruction word of the 5ubstract instruction, which is the second instruction, is stored in the instruction register 112.

Therefore, “5” in the R1 field of the first instruction is applied to the signal line 582, and “5” in the X2 field of the second instruction is applied to the signal line 524.

Since it is assumed that there is no register conflict I- except for the first and second instructions, the signal lines 558 and 526 are
5" is being applied.

Therefore, the output of the minus number comparison circuit 160 becomes "1", and the outputs of the other match comparison circuits 162, 1.64, and 166 become "0". Therefore, the output signal line 593 of the OR circuit 168
becomes [1]. In addition, the output signal line 5910 of the OR circuit
Output signal line 596 of R circuit 182. Output signal line 590 of AND circuit 172 Output signal line 590 of AND circuit 174. AN
The output signal line of the D circuit 180 becomes rOJ.

Since the signal line 592 is "0" and the signal line 593 is "1", no significant data is output to the signal line 54O. On the other hand, selector 3]8 is the second selector on signal line 536.
The B2 register value of the instruction is applied to the address adder 324 via the signal line 542.The displacement of the second instruction is applied to the address adder from the signal line 528. As a result, the operand address of the second instruction is stored in the operand address register 120 at time T4.

Also, IRI register 124. ICI register 130.
0RX Lujista], 32. GItB Lujista 134.
The same data as the operation when there is no register conflict 1 to 1 is stored in the IFΔ register 13G at time T4.

In the subsequent operation of the second instruction, since no significant data is output on the register conflict signal line 540, the address adder 548 does not output any significant data. Therefore, even at time T4, the operand address register 12
No significant data is stored in 0. Also, IRI register I24°ICI register 130. GRXI register 13□2゜GRB register 134. IFA register 1
Data that is also present in 36 is not stored.

On the other hand, at time T4, the first
The instruction word of the Ad4 instruction, which is an instruction, is stored. At this time, the output of the minus number comparison circuit 164 becomes rlJ, and the output of the other coincidence comparison circuits 160, 162, . The output of 166 is rO
Become J. Therefore, the output signal line 593 of the OR circuit 168 and the output signal line 584 of the AND circuit 180 become [1].

Furthermore, the output signal lines 591 and 5 of the OR circuits 170 and 182
96 and the output signal line 592 of the AND circuits 172 and 174.
590 becomes "0". At this time, the signal line 592 is also “0”
Since the signal line 593 is "1", no data is output on the signal line 540.

Since no significant data is output on signal line 540), address adder 548 does not output significant data. Therefore, no significant data is stored in the operand address register 20 even at time T5. Also, 1R
]Register 1.2/l, 1. C Lujista 130. GRX
]Register 132. GRBI register 134. No significant data is stored in the IFA register] or 36.

On the other hand, at time T5, no significant data is stored in the 1R-2 register 138. At this time, the outputs of the match comparison circuits 160, 162, 1.64, and 166 become "0". Therefore, signal lines 590, 591. 592, 593, 5
84.596 jumps and yells "0".

As a result, the selector 31G selects the second signal line 534''.
The X2 register value of the address is applied to the address adder 324 via the signal line 540, and the selector 318 is applied to the address adder 324 via the signal line 540.
361 second address B2 register value from the signal 54
2 to the address adder 324. signal line 5
From 28, the displacement of the second address is applied to the address adder.

As a result, the operand address of the second address is stored in the operand address register 120 at time T6.

Also, the IR] register 124. ICI register 130
, GRXI register 132. GRBI register 134.
, IFAI register 136 contains register conflict 1.
The same data as in the operation without ~ is stored at time T6.

The subsequent operation of the second address is the register configuration IJRI1.
・Proceed in the same way as in the case where there is no problem.

Calculation of 171st-response from time T 4?ALU 3
30, and the calculation result is applied to the continuous storage device via the signal line 556 between times T4 and T5.

Further, "1" on the belief line 5841 is outputted to the associative memory device. As a result, the IC storage section 346 of the associative memory device 346. IR storage section 348. X2 register value storage section 35
0. B2 register value storage section 352. Prefetch instruction address record/arm section 354. The prediction data storage unit 35G stores the instruction address l of the first instruction on the signal line 580 (the first instruction word on the i-band line 564, and the X of the first instruction on the signal line 578).
2 register value, the B2 register value of the first instruction on signal line 576, and the word that is the operation result of the first instruction on signal line 556, the prefetch instruction address when prefetching the first instruction on signal line 574, at time T5. be registered.

Furthermore, this concludes the description of the case where the associative memory does not have information from a previous run.

Next, effects specific to this embodiment will be described.

When the present invention is not used, if a subsequent instruction with a register conflict I- is executed with the preceding instruction, the operation will be the same as when there is no information about the previous execution in the associative memory device described above, and two periods of idle time will be used. arise.

With this invention, there will be no free time at all,
Improves instruction processing performance when a register conflict occurs.

The above-described embodiment uses the calculation result of the previous execution of the preceding instruction as the predicted value of the calculation result of the preceding instruction. However, the present invention also applies to the case where the result of performing an operation on part of the operand data from the previous execution of the preceding instruction and the remaining operand data obtained during execution is used as the predicted value of the operation result of the preceding instruction. Applicable.

FIG. 10A is an overall configuration diagram of the embodiment in this case.

figure Shown in 10th BJt, l'.

The associative memory shown in this figure stores the second operand data of the preceding instruction instead of the operation result of the preceding instruction. When the preceding instruction is executed, the associative key causes the associative memory to output the second operand data from the previous execution to signal line 538. The opcode of the preceding instruction is sent to the ALU via the signal line 604.
The R1 register value of the preceding instruction is selected by the selector 362 to which the R1 field is applied and is input to the ALU 360 via the signal line 606. As a result, the predicted value is output to the signal line 600, and subsequent instructions are executed without any idle time.

In the above embodiment, the predicted value and the calculation result are directly compared, but the operand data output from the continuous storage device and the operand data obtained at the time of execution may be compared.

FIG. 11A is an overall configuration diagram of the embodiment in this case.

Shown in FIG. 11B.

The second operand at the time of execution of the preceding instruction is input to the left input of the comparator 332 in this figure via the signal line 554, and the second operand output from the associative memory device via the PDSV register 54 is input to the right input. are being compared.

With this method as well, the same result as the comparison result between the predicted value and the calculation result performed in the above embodiment can be obtained on the signal line 586.

In the embodiment described above, the look-ahead address of the preceding instruction, the instruction address, and the recall address are used as the associative keys. However, the present invention can be applied even if the instruction address and the read-ahead address before the preceding instruction are avoided.

In this case, a delay register may be provided immediately before the IC register 30 on the signal line 544 and the signal line 530. As a result, at the time of registration, the prefetch address and the instruction address of the instruction before the preceding instruction are written into the associative memory device, so that they can be used as an associative key.

Further, as the associative keys, all of the above-mentioned keys can be used, or any combination can be used. In this case, it is also possible to use some bit positions of the key components.

〔Effect of the invention〕

If the present invention is not used, it takes address calculation time, operand read time, and operation time for the preceding instruction after the preceding instruction that causes register conflict 1 to starts is started until the subsequent instruction is started.

However, by using the present invention, it only takes time from inputting the associative key to the prediction device to outputting the predicted value. The latter time varies depending on what is used as the associative key, but even in the worst case where the instruction address of the preceding instruction is used as the associative key, the time is sufficiently shorter than when the present invention is not used.

[Brief explanation of drawings]

Figure 1A is an instruction format diagram, Figure 1B is an example of a load instruction, Figure 2 is an example of two instructions that cause a register conflict,
3A and 3B are general configuration diagrams of the embodiment, FIG. 4 is a configuration diagram of an associative memory device, FIGS. 5 to 8 are timing chart diagrams, and FIG. 9 is a configuration diagram of a register conflict detection device.
FIG. 10A, FIG. 10B, and FIG. 11A, FIG. 11B are overall configuration diagrams of other embodiments, respectively. Explanation of symbols 100...Prefetch instruction address register 304...
Instruction storage devices 104, 106, 108, 110...instruction buffer 1
12...Instruction register 114...Instruction counter 324...Address adder 120...Operand address register 326...
Operand storage device 126...operand data register 330...A
LU 118...Register file 320...Prediction device 322...Register conflict detection device Figure 1A No. 18 0pR1, Dz (Bit, Xz) Figure 2 ■ A 5.100 (j, 2) ■ S 8, 150 (7, 5) ■h Fig. 8 IFAD []] = “----- vsv Signal #I58 Otsuzume 9 Fig.

Claims (1)

[Claims] 1. When a subsequent instruction is executed using the operation result written to the register by the preceding instruction, the processing of the subsequent instruction does not include the operation result until the operation result is determined. An instruction address of the preceding instruction, an instruction address of the instruction before the preceding instruction, a pre-reading address when prefetching the preceding instruction, and a pre-reading address when prefetching the instruction before the preceding instruction in the information processing device that stops the processing used. a prediction device that predicts the operation result of the preceding instruction by using a look-ahead address, the contents of a register referred to by the preceding instruction, or the preceding instruction word as an associative key; a device for detecting whether a prediction device outputs a predicted value of the operation result of the preceding instruction, and starting the stopped process using the predicted value when detected; Information having a device that verifies whether the result of the operation written to the register is equal to the result of the operation written to the register, and a device that restarts the subsequent instruction using the result of the operation written to the register by the preceding instruction when the verification result does not match. Processing equipment. 2. The information processing device according to claim 1, wherein the prediction device uses a calculation result from a previous execution of the preceding instruction as the predicted value. 3. The operation result of the preceding instruction is obtained as a result of performing an operation on one or more operand data of the preceding instruction, and the prediction device contains operand data from previous execution of the preceding instruction. A part of the operand data is stored, and when the preceding instruction is executed, the result of performing an operation on the stored part of the operand data and the remaining operand data obtained at the time of execution is calculated as the pre-i1+! 2. The information processing device according to claim 1, wherein the information processing device is used as a predicted value for a device. 4. A part of operand data from a previous execution of the preceding instruction stored in the prediction device as a device for verifying whether the predicted value is equal to the operation result written to the register by the preceding instruction; 4. The information processing apparatus according to claim 3, further comprising a device for comparing part of operand data obtained during execution of the preceding instruction.