WO1998011484A1

WO1998011484A1 - Command processor having history memory

Info

Publication number: WO1998011484A1
Application number: PCT/JP1996/002633
Authority: WO
Inventors: Yukio Umetani; Yoshio Miki
Original assignee: Hitachi, Ltd.
Priority date: 1996-09-13
Filing date: 1996-09-13
Publication date: 1998-03-19

Abstract

A command processor having history memory that contains data obtained when commands were executed in the past, such as input data with the arithmetic results and read/write addresses with data at the addresses, wherein the history data are referred to so as to speed up execution of the same commands. If the history remains, the current input data and the history data are compared for arithmetic operation, while the current read/address data and the addresses are compared for read/write operations. If a coincidence occurs, the arithmetic operation is skipped and the history data is used, while the read/write operation is skipped. This increases the speed of processing and reduces the number of pipeline stages necessary for executing each command, so that the execution time of a command string can be shortened and an unnecessary load/store operation for the memory can be eliminated. In consequence, the memory management such as cache control and address conversion can be efficient, and the mean execution time of the load/store command can be shortened.

Description

/ JP96 / 02633

1

Specification

Instruction processing device with history storage

The present invention relates to the configuration of an instruction processing device, and more particularly to an instruction processing device that uses an execution history to increase the speed. Background art

As a technology in this field, a cache memory control technology using the address history of data and instruction words is widely known, and a technology for increasing the accuracy of prediction using the branch instruction establishment history (Japanese Patent Application No. No. 3,400,266, etc.) are known. As is well known, the cache memory is a small-capacity high-speed memory placed in order to reduce the access time to the main memory. When a processor reads data or an instruction from the main memory, the address and data or the instruction are read. Is registered in the cache memory. When the processing unit accesses the main memory, it first refers to the cache memory, and accesses the main memory only when no data or instruction is registered there. Since the address history of data and instruction words is recursive, pairs that have been registered in the cache memory once have a high probability of being referenced again. Can be effectively shortened. When writing data or instructions to the main memory, the contents of the main memory and the cache memory are matched by invalidating or rewriting the corresponding pair of the cache memory. Ma When the cache memory becomes full, one of the registered pairs is deleted to make room. Regarding the branch instruction establishment history, the number of successful or unsuccessful branches is stored in a special storage device for each address of the branch instruction, and the information is read by prefetching the instruction of the path with a high possibility using the information. Stochastically reduce time.

Also, Japanese Patent Application Laid-Open No. 60-129,839 discloses a technique for speculatively starting the execution of an instruction using the result of a load instruction before the execution of the instruction is completed. A history record is used to store the address of a spoken command and data previously read from main memory as a pair.

However, in the above-described conventional technology, the use of the history information is limited to the reduction of the main memory access time or the speculative start of instruction execution, the calculation time performed in the processing device, the address calculation time, and the cache memory. Not used to reduce access time.

It is an object of the present invention to provide a history storage device which can reduce such time. Another object of the present invention is to provide a storage management method in which valid information is stored in history storage. Disclosure of the invention

For this reason, in the present invention, the validity of operation input and result data, the load / store address and data of main memory, the contents of the register forming the address, and the history are determined in correspondence with each executed instruction address. Prepare a history storage (HS: History Storage) that selectively stores the success count shown, and execute the instruction of the same address again. When the history is left, the current input data is compared with the history data in the case of the operation instruction, and in the case of the read Z write instruction, the current read / write data is The addresses are compared with the history, and if they are the same, the execution of the operation is skipped in the case of the operation instruction, and the result data of the history storage is used as the current result, and in the case of the load store instruction, the cache memory is used. By skipping the access to the command, the speed-up is achieved by using the result data of the history storage as the current result in the spoken instruction. In the load store instruction, if the contents of the registers forming the address are equal to the current value and the history value, the calculation of the address is also skipped. The number of successful skips is reflected in the history's success count, and when there is no more space in the history storage, information is deleted in ascending order of success count so that effective information remains in the history record. In order to maintain consistency between the history storage and the contents of the cache memory and main memory, the history storage has an invalid display field corresponding to the instruction address, and is written to the instruction address or the word address in the history storage. In such a case, the corresponding part is invalidated.

Specifically, the instruction processing device processes an instruction specified by an address. When executing the instruction, the instruction processing device stores, as history information, a pair of data processed by the instruction and an address of the instruction. A history storage device for executing the instruction, a recording unit for recording the history information in the history storage device when executing the instruction, and a content of the history information stored in the history storage device when the instruction of the same address is executed again. Re-executing means for executing the instruction with the use of: and updating means for updating the content of the history information stored in the history storage device when re-executing the instruction at the same address. This is achieved by an instruction processing device having the same.

In the above-mentioned instruction processing apparatus, when the instruction is an operation instruction, the data includes data that is an input of an operation and data of an operation result, and the re-executing unit is configured to execute the operation at the present time. A comparator for comparing data serving as an input of the operation of the instruction with data serving as an input of the operation of the operation instruction recorded in the history storage device; and the history storage device when the comparator indicates a match. This is achieved by having means for using the data of the operation result recorded in the operation instruction as the operation result data of the operation instruction at the current time. Further, when the instruction is a store instruction, the data includes a store destination address and a store data accessed by the store instruction, and the re-executing means stores the store instruction of the store instruction at the present time. A first comparator for comparing a store destination address with a store destination address of the store instruction recorded in the history storage device; and a store data of the store instruction at the present time and the storage data stored in the history storage device. A second comparator for comparing the stored data of the store instruction with the stored instruction of the store instruction, and a store of the current store instruction when the first comparator and the second comparator both indicate a match. This is achieved by an instruction processing device having means for suppressing operation.

Furthermore, the re-executing means has means for executing a store instruction at the present time when the first comparator and the second comparator do not show a match, and in this case, the updating means Is achieved by an instruction processing device for invalidating the data in the history storage device having the storage destination address.

Further, when the instruction is a store instruction, the data includes the contents of an address register group forming a store address and a store address, and The comparing means for comparing the content of the address register group at the current time with the content of the address register group recorded in the history storage device; and calculating the destination address when the comparing means indicates a match. And an instruction processing device having means for using the store destination address recorded in the history storage device. The re-executing means includes means for executing a store instruction at the present time when the comparing means does not indicate a match, and in this case, the updating means includes a memory for executing the store instruction having the store destination address. This is achieved by invalidating the data in the history storage device.

Further, when the instruction is a load instruction, the data includes a load source address and load data to be accessed by the load instruction, and the re-executing means includes a load source address of the load instruction at a current time. And a first comparator for comparing the address and the load source address of the above-mentioned instruction stored in the history storage device. Means for converting the read load data into load data by execution of a currently executed instruction.

Further, when the instruction is a load instruction, the data includes the load data and the contents of a group of address registers forming a cache address, and the re-executing means includes: Comparing means for comparing the contents of the address register group with the contents of the address register group of the confidential instruction recorded in the history storage device; and The present invention is achieved by an instruction processing apparatus having means for using the recorded load data as load data of a result of a click operation of a current click command. Further, the history information recorded in the history storage device has a counter for counting the number of times the re-executing unit has executed the command using the history information, and the updating unit includes: Means for updating the counter when an instruction is executed using the history information, and means for deleting the history information in ascending order of the counter value when the storage area of the history storage device is insufficient. This is achieved by an instruction processing device having Also, the instruction processing device executes the instruction without using the history when the history storage device does not have the history information on the instruction when executing the instruction, and newly stores the history information on the instruction in the history storage. Achieved by registering with the device. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing an overall configuration according to the present invention. Figure 2 is a detailed configuration diagram of the general-purpose operation unit. FIG. 3 is a detailed configuration diagram of the floating-point operation unit. FIG. 4 is a detailed configuration diagram of the branch operation unit. FIG. 5 is a diagram illustrating an example of an instruction sequence. FIG. 6 is a diagram showing an execution stage flow of an instruction sequence. Figure 7 shows an alternative to the overall configuration. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 shows the configuration of the target instruction processing device. The instruction processor has an instruction cache memory 11 that temporarily stores instructions, an instruction control unit 12 that controls instructions in the instruction processor, a branch operation unit 13 that performs branch operations, and fixed-point instructions. mouth It comprises a general-purpose operation unit 14 for executing a 1-d Z store instruction, a floating-point operation unit 15 for executing a floating-point operation, and a data cache storage 16 for temporarily storing data. Although the main storage device is not shown in FIG. 1, instructions and data to be processed by the instruction processing device are stored in the main storage device. The instruction control unit 12 and the operation units 13, 14, and 15 transfer the above-described instruction and data to and from the main storage device via the instruction cache 11 and the data cache 16.

The instruction sequence is read from the instruction cache memory 11 to the instruction buffer 12 in the instruction control unit 12 by the instruction control unit 12, and the branch operation unit 13 and the general-purpose operation unit are executed for each instruction type. 14. Floating-point operation unit 15 and then executed by each operation unit. Dotted lines indicate the flow of command words. The branch operation unit 13 has an instruction queue (IQB) 133 that receives the distributed partial instruction sequence, a history storage (HSB) 135 that records the history data of the executed instruction along with the instruction address of the instruction, and an instruction queue. The history queue (HQB) 134 that stores history data corresponding to the instruction of instruction, the instruction processing unit (Br) 136 that performs branch operation, the history processing unit (HeVB) 131, and the condition code (CC) 132 is included.

The general-purpose operation unit 14 has an instruction queue (IQG) 143 that receives the sorted partial instruction sequence, a history storage (HSG) 145, and a history queue (HQG) that holds history data corresponding to instructions in the instruction queue 143. 144, Instruction processing unit (Fixed) 146, History processing unit (He vG) 141, and general-purpose register (GR) 142 are included. The floating-point arithmetic unit 15 has an instruction queue (IQF) 153 for receiving the divided partial instruction sequence, a history storage (HSF)] 55, and a history queue (Histogram for holding history data corresponding to the instruction queue). HQ F) 154, instruction processing unit (F 1 oat) 156, history processing unit (H ev F)] 51, and floating point register (FR) 155.

FIG. 2 shows a more detailed configuration of the core general-purpose arithmetic unit 14.

The instruction queue (IQG) 143 is a storage means for temporarily storing instructions, and an instruction address field (I adr) 1 43 1 for storing the address of the instruction in main memory for each instruction. , Instruction code field (Op) 1 432, Field for holding the operation input register or load register address register number (S1, S2) 1 433, 1434, Operation result or load store data It consists of an (R) field 1435 that holds the register number. The register number values in fields 1433, 1434, and 1435 are used to specify the registers in general-purpose registers 142a and 142b. The instruction address is stored when the instruction is registered in the instruction queue. Note that, in the general-purpose registers 142a and 142b, r0 and r31 indicate register numbers. In the figure, r2 to r30 are omitted.

History storage (HSG) 145 is a storage device for storing a history of executed instructions, and stores history information on instructions executed in instruction units. The history information includes, for each instruction, an instruction address field (I adr) 1451 for storing the address of the instruction in the main memory, and a condition code field for storing a condition code of an instruction execution result. (CC) 1 452, operation input data or address register contents field (D ata SD ata S 2) 1 453, 1 454, operation result or data loaded from main memory Field of store data to be stored in the main memory (Data R) 1 455, Load store address field (D adr) 1 456 for storing the source or destination address in main memory A counter that records the number of times the history information has been used effectively during instruction re-execution. The effective count field (Cnt) 1 used to determine the history information to be deleted when there is no more free space in the history storage 457, an invalidation field (I) 1458 that displays the result of store cancellation. The instruction address in the main memory is registered when a new instruction execution history is added to the history storage. The line for writing the instruction address to the history storage is omitted from the figure.

The history queue (HQG) 144 has a V field (V) 144 1 that indicates the presence or absence of history information, a condition code history field (CC) 1 442, and operation input data or an address register corresponding to each instruction in the instruction queue. History field of data contents (D ata S l, D ata S 2) 1443, 1444, History field of data stored in the register data (Data R) 1445, Rhodes The history field of the address (Dadr) consists of 1446. When an instruction is registered in the instruction queue, if the history of the instruction corresponding to the registered instruction is stored in the history storage 145, the history of the instruction corresponding to the registered instruction is stored in the history queue. Copied from history memory 145.

Instructions stacked in the instruction queue 143 are pipelined in order from the bottom in FIG. Scheduled and executed. The operation instruction bi-line is read from the register.

It consists of three stages: (r), arithmetic operation (a), and register write (w). The pipeline of the load instruction consists of four stages: address register read (r), address calculation ( _a ), data load (L), and register write (w). The store instruction bipline consists of four stages: address register read (r), address calculation ( _a ), data read (r), and data store (ST). The instruction word registers 2 1 1, 2 1 2, 2 1 3, and 2 1 4 are registers for storing instruction words executed in the first to fourth stages, respectively. 2 3 3 and 2 3 4 correspond to the second to fourth stages of the instruction word register, respectively, and a part of the history information of each stage (result data or password Z store data and password z store address). ) Is a register that stores. Scheduled command and history information flows sequentially through these registers. The line indicating the movement of data from the history register 23 3 to the history register 23 4 is omitted from FIG.

The storage means 201 to 204 hold a bit (V bit) indicating the presence or absence of history for each stage. The storage means 26 2, 26 3, and 26 4 hold a bit (U bit) indicating the validity of the history determined in the first stage from the second stage to the fourth stage. The movement of U-bit data between storage devices from the second stage to the four stages and the movement of V-bit data between the storage devices from the second stage to four stages are omitted from FIG. The U bit is set to "1" when the input data of the history or the contents of the address register are all equal to the input data of the corresponding current instruction or the contents of the address register. Otherwise, it is set to "0". Two comparators 2 4 1 a, 2411b (first and second comparators) are used for determination when setting the U bit, and the U bit is the output of the two comparators and the V bit ( The value of the logical product of the output of 2 0 1). An AND circuit 251 is used to calculate the AND. The general-purpose registers 1442a and 1442b are used to hold both fixed-point data and memory addresses. The two general-purpose registers 1 4 2 a and 1 4 2 b hold the same data and store the contents of the number specified by the instruction word into the general-purpose operation unit address Z data register 2 2 2 a and 2 2 b. Via the fixed-point arithmetic unit 146. Register 2 42 holds the condition code CC generated as a result of the operation, and result register 2 23 holds the result of the second stage operation or address calculation (Adr ZD ata).

The address register 224a is a register that holds the address generated in the second stage by the load store instruction in the third stage, and the register 224b is the memory (main memory, data) by the load instruction. This register holds the data read from the cache or the store data read from the register by the store instruction. The third comparator 243 is used for comparing the load destination address of the data of the current instruction with the load destination address of the history data in the load instruction. The fourth and fifth comparators 244a and 244b respectively compare the value of the current instruction with respect to the write data (store data) with the history value and store the write address (main memory) by the store instruction. This is used to compare the value of the current instruction with respect to the storage address of the current instruction and the history value. The AND circuit 254 is a circuit that calculates the logical product of the comparison result of the two.

The procedure for using and generating history information using these configurations is as follows. You. First, when registering an instruction in the instruction queue 144, the instruction address 143 1 is used as a key to search the history record 145, and if found, the V field of the corresponding entry of the history queue 144 1 Is set to "]", and the corresponding information in the history storage is copied to the information field of the history queue 144. When the history memory 145 is searched using the instruction address 1431 as a key and cannot be found, the V field is set to "0 (zero)" to set that there is no history data in the instruction.

Next, in the first stage, the current instruction value of the input data or address and the history value are compared by the comparators 24 1a and 24 1b. More specifically, first, the data of general-purpose registers 142a and 142b, designated by the address register numbers S1 and S2 of the instruction word register 211, are connected to the lines 2101 and 2102, respectively. read out. Also, read Data S 1 and Data S 2 from the history queue 44. The comparator 241a compares the Data 201 1 with the Data S 1 and outputs whether or not they match to the AND circuit 251 via the line 2103. Similarly, D ata 2 l 02 and Data S 2 are compared by the comparator 241 b, and whether they match is output to the AND circuit 251 via the line 2104. The AND circuit 251 ANDs the result from the comparators 241 a and 241 b and the V value in 201. When the results from the comparators 24 1a and 24 1b both indicate a match and the V value in 201 indicates valid, the U bit is determined as a match between the current instruction value of the input data or address and the history value. "1" is set.

When the U value is set in the AND circuit 25 1 and U is "1", that is, when the instruction has history data and the current value of the input is equal to the history value, the line 2 2005, update the effective count of the current instruction in the history record via the line 2003.

The processing for each instruction type when is "1" is described below.

If the instruction is an arithmetic instruction, the second stage is skipped, the instruction word of the third stage is stored in the instruction register 2 13, and the history information (CC, DataR, ). The history information sent to the history register 233 is written as (HCC, HDDataR, HDDadr) to distinguish it from the contents of the history queue HQG. In the third stage, the operation is completed by writing the result data (HDatR) of the history register 233 to the designated numbers of the general-purpose registers 142a and 142b via the line 2301 and the line 2001.

If the instruction is a store instruction, the second stage is skipped and the instruction is sent to the instruction register 2 13 of the third stage, and the history information is sent from the history queue 144 to the history register 233. In the third stage, store data is stored in register 224b (the contents of general registers 142a to 142b specified by the field R of the instruction. 42b is written as a general-purpose register G r, and store data is input from this G r), and then proceed to the fourth stage. In the fourth stage, the comparator 244a compares the current value of the store data with the history value HD ata R, and if both match, the store operation is suppressed. This has the effect of shortening the execution time of the store instruction. When the comparison results do not match, a normal store is performed, and the address (HAdr) in register 234 and the data in register 224b are transferred via lines 2406, 2402, and 2002. History record 1 Write to the corresponding entry of 45. If there is an entry having the same address as the storage address in the history storage No. 45, the invalidation field 14457 is set to "1". This erases the history of previous store instructions with the same store address.

If the instruction is a load instruction, the second and third stages are skipped, the instruction word of the fourth stage is stored in the instruction word register 214, and the history information is stored in the history register 234 from the history queue (CC, DataR). , D adr). In the load instruction, in the fourth stage, the read data (HDa R) of the history register 234 is written to the general-purpose registers 142a and 142b via the lines 2403 and 2001, or the floating-point register 1 in FIG. Send to floating point unit 15 via line 2405 to write to 52a, 152b and terminate the instruction (in FIG. 2, the floating point unit is denoted by Fu).

The processing for each type of instruction when is "1" has been described above. Next, the processing of each instruction when U does not stand in the first stage (when U = 0) is described.

In the case of an operation instruction, in the second stage, the operation input data of the registers 222a and 222b are registered in the history storage 145 via the line 2201, and the operation is performed in the instruction processing unit 146. Is stored in the register 223. The operation result is written from the register 223 of the third stage to the general-purpose registers 142a and 142b via the lines 2302 and 2001, and is registered in the history storage 145 via the line 2002. In the case of a spoken instruction, the load source address is calculated in the second stage, the calculated load source address is stored in the register 223, and is indicated by the address stored in the register 223 in the third stage. Start reading data from main memory (including data cache) to register 224b. At the same time, when the V bit 203 is ON ("1") and there is history information, the comparator 243 compares the current address from the register 223 with the history address Hadr from the 233. I do. As a result of the comparison of the load source address by the comparator 243, when the two match, the data reading is canceled (load suppression) and the effective count of the history storage via the lines 2304 and 20033 is performed. Update 1 4 5 7 Also, set the U bit 264 of the fourth stage to "1". In the fourth stage, the U bit 264 power; when "1", the result data (Hdata R) on the history register 234 is transferred to the general registers 1442a and 1442 via lines 2403 and 2001, respectively. b or sent to floating point unit 15 via line 2405 to write to floating point registers 152a, 152b in Figure 3. If the load source address does not match as a result of the comparison by the comparator 243, the read data obtained in the register 224b using the load source address stored in the register 223 and the V bit 204 are turned on. When Compared with the history data HD ata R in the history register 234 using the comparator 244a. When the two data match, the effective count of the history record is updated via the lines 2404 and 2003. Read data on register 2 24b is written to general registers 144a, 142b via lines 2402, 2001, or to the floating-point registers 1552a, 152b in Figure 3 Float It is sent to the floating-point operation unit 15. Also, the address on register 2 24 a and the data on register 2 24 b are written to history storage 1 45 via lines 240 1, 240 2, and 200 2 to store the history information. Update.

In the case of the store instruction, the address calculation is performed by the second stage computing unit 146, and in the third stage, the calculated address is stored in the register 224a and stored in the general-purpose register indicated by the store instruction. Set the data in register 2 2 4b. In the fourth stage, the current value of the data and the history value are compared by the comparator 244a, the current value of the address and the history value are compared by the comparator 244b, and the logical product of the comparison results is obtained. Is taken by the AND circuit 2 5 4. When both the current value and the history value of the address and data match, that is, in this case, since the store data is stored at the store destination address, the store operation is suppressed. Since this store operation is suppressed, the execution time of the store instruction can be reduced. If both the current value and the history value do not match for the address and data, store normally. The address and data are written to the corresponding entry of the history storage 145 via the lines 2401, 242, and 202. If there is an entry in which the content of the data address field 14456 of the history storage 144 matches the address, the invalidation field 14457 is set to "1".

The processing of each instruction when U does not stand in the first stage (when U = 0) has been described above.

In FIG. 2, if there is no empty entry at the time of registration to the history storage 1 45, a space is created by deleting the effective counts 1 4 5 7 in ascending order to create a valid history information. Control is performed so that the information remains. As a result, of the history storage, those that are frequently reused remain and are deleted from the history information that is not frequently reused, so that the area of the history storage can be used effectively. it can.

FIG. 3 similarly shows a detailed configuration of the floating-point operation unit 15. Since load Z store instruction is not handled here, it is simpler than that in Fig. 2.

First, the symbols in Fig. 3 are summarized as follows. 301, 302, and 303 are stage V bits in the floating-point operation unit, and 311, 312, and 313 are instruction word registers for storing the instruction words of each stage in the floating-point operation unit. , 322a, 322b, and 323 are data registers in the floating-point operation unit, 332 and 333 are stage history registers in the floating-point operation unit, and 341a and 341b are data in the dynamic point operation unit. 342 is a condition code register in the floating-point operation unit, 351 is an AND circuit in the floating-point operation unit, and 362 and 363 are stage history valid bits in the floating-point operation unit. Yes, 3001, 3002, 310, 310, 3201, 3301, 3302, and 3303 are lines in the floating operation unit.

The instruction queue (IQF) 153 is a storage means for temporarily storing instructions. For each instruction, an instruction address field (I adr) 1 53 1, an instruction code field (Op) 1 532, and an operation It consists of fields (S1, S2) 1533 and 1534 that hold the address register number of the input register, and a field (R) 1535 that holds the register number that stores the operation result. The register number values for fields 1 533, 1 534, and 15 35 are the floating point registers 1 52a and 1 52b registers ^ Used to specify.

The history storage (HSF) 155 is a storage means for storing the history of execution, stores history information registered for each instruction, and stores an instruction address field (I adr) 155 1 for each instruction and a condition code field. (CC)] 552, Finoredo of operation input data (DataSl, DataS2) 1 553, 1554, Field of operation result (DataR) 1555, Effective count (Cnt) Field 1 consists of 557.

The history queue (HQF) 154 has a V field 154 1, which indicates the presence or absence of history information, the condition code history field (CC) 154 2, and the contents of operation input data for each instruction in the instruction queue. History fields (D ata S l, D at _a S 2) 1 543 and 1 544, and a history field (D ata R) 1 545 of the operation result. When an instruction is registered in the instruction queue, if the history of the instruction corresponding to the registered instruction is stored in the history memory 155, the history of the instruction corresponding to the registered instruction is stored in the history queue. History memory 1 Copied from 55.

There are three pipeline stages: floating point register reading (ir), floating point operation (ia), and floating point register writing (fw). The instruction register 311, 312, 313 holds the instruction of each stage. The information held in the history register is only the condition code and the value of the result register.The history register 332 holds the history of the instruction of the second stage, and the history register 333 stores the history data of the instruction of the third stage. Hold. The comparators 34 1 a and 34 1 b are used for comparing the operation input data with the history value of the history queue. The operation of each component shown in FIG. 3 when the floating-point operation instruction in FIG. 3 is executed is the same as the operation of each component shown in FIG. 2 corresponding to the component shown in FIG. This is the same as the operation at the time of execution of the operation instruction in FIG.

FIG. 4 shows the detailed configuration of the branch operation unit 13.

First, the symbols in Fig. 4 are summarized as follows. 401, 402 are stage V bits in the branch operation unit, 411, 4] and 2 are instruction word registers for storing stage instruction words in the branch operation unit, and 431, 432 Is a stage history register in the branch operation unit, 441 and 452 are condition code registers in the branch operation unit, 442 is a branch establishment register, 461 is a branch address addition circuit, and 462 is a branch address addition circuit. A branch address register, 471 is a branch operation unit / comparator, 472 is a branch operation unit history valid bit, and 4022 and 4003 are lines in the branch operation unit.

Each line of the instruction queue (IQB) 133 has an instruction address field (Iadr) 1331, an instruction code field (Op) 1332, a branch mask field (M) 1333, and a branch destination relative address field (Tadr). Consists of 1 334. The history queue (HQB) 134 has a V field 1341 indicating the presence / absence of history information, a condition code field (CC) 1 342, a branch destination address (Badr) corresponding to each instruction in the instruction queue. 1) Hold 343. History storage (HS B) 1 35, the instruction address field _{(I a dr) 1 35 1} , condition code field (CC) 1 3 52, branch destination Adoresu (B adr) 1 353, the effective count field (C nt) 1 Consists of 354. The pipeline consists of two stages: branch address calculation (ba) and branch (bb). The instruction registers 4 1 1 and 4 1 2 hold the instruction word of each stage, and the history registers 43 1 and 432 hold the history information corresponding to those instructions.

In the first stage, the condition code (CC) 441 sent from the general-purpose arithmetic unit (Gu) 14 or the floating-point arithmetic unit (Fu) 15 is used for the instruction in the instruction register 4 11 1. The word mask is compared with the comparator 451 to determine whether or not there is a branch, and the result is set in the register 442. On the other hand, the branch address is determined from the instruction address and the branch destination relative address using the address adder 461 and set in the branch address register 462. Also, the condition code (HCC) of the history register 431 is compared with the condition code of the register 441 using the comparator 471, and the result is set in the history valid bit (U bit) 472.

In the second stage, when the branch is taken, the condition code of register 452 and the branch address of register 462 are registered in history storage 135 via line 4002, and when U bit 472 is "1", line 4003 Update the effective count (Cnt) field 1354 of the corresponding instruction in the history store 135. Further, when the branch is taken, the branch address of the register 462 is sent to the instruction cache 11 to read the branch destination instruction.

The process of executing an instruction sequence using the configuration described above will be described based on an example of the instruction sequence shown in FIG. First, an example of an instruction sequence will be described with reference to FIG.

In the instruction sequence in Fig. 5, the leftmost column is the instruction number ((1) (2) · · · (1 4)), the right is the branch destination label (L0), and the next column is the instruction code. C (LD I, SUB, etc.) , And the following columns indicate the operands (],% r 9, etc.). In the operand field,% r indicates a general-purpose register, and% ir indicates a floating-point register. The registers at the right end indicate the registers where the results are placed by operation instructions and load instructions, and the others indicate registers for operation input, store data, or address specification. Numerical value means direct designation of data or address by command word.

Instruction numbers (1), (2), (4), (6), (7), (8), and (11) are fixed-point arithmetic instructions, which are executed by the general-purpose arithmetic unit. Instruction numbers (3) and (14) are fixed-point load instructions, also executed by the general-purpose arithmetic unit. Instruction numbers (5), (9) and (12) are floating-point load / store instructions, which are executed by the general-purpose operation unit 14 and the floating-point operation unit 15 in cooperation. The instruction number (10) is a floating-point operation instruction, and is executed by the floating-point operation unit 15. Finally, the instruction number (13) is a comparison / branch instruction, which is executed by the general-purpose operation unit 14 and the branch operation unit 13 in cooperation.

The function of each instruction is as follows.

The LDI (Load Immediate) instructions (1) and (2) transfer the value directly to the result register. In the example of the instruction (1), the value 1 is transferred to the general-purpose register 9. The LDW (Load Word) instructions in (3) and (14) are the fixed-point data for one word from the memory address specified by the sum of the contents of general-purpose register 30 and the direct value 604. And set it to general-purpose register 3 No. 1. The (4), (7) and (11) LDO (Load Offset) instructions add the specified offset value directly to the contents of the end address register and set it in the result register. In the example of (4), from the contents of general-purpose register 9; , And set the result in general-purpose register 6]. The (5) and (9) FLDDX (F) loading L Double (ndexed) instructions read the floating-point data from the memory address to which the contents of the two address registers have been added, and set them in the result register. . In the example of (5), data is read from the address obtained by adding the contents of general-purpose registers 16 and 16 to the contents of general-purpose registers 2 and 2 and set to the floating-point register 8. (6) is a fixed-point arithmetic instruction. In the example of (6), the contents of general registers 23 and 23 are subtracted from the contents of general registers 8 and the result is set to general registers 17 and 17. (8) is an addition instruction. (10) is an instruction that multiplies the contents of the floating-point register 7 and the contents of the floating-point register 8 and sets the result in the dynamic-point register 13. The FS TDX (Floating Store Double Indexed) instruction of (1 2) stores the contents of floating-point register 13 into a memory address that is the sum of the contents of general-purpose register 20 and general-purpose register 26. I do. The (13) COMB (Compare and Branch) instruction compares the contents of general-purpose register 9 and general-purpose register 11 and has the L0 label when the latter is greater than or equal to the former. Branch to instruction. That is, this instruction sequence creates a loop. The instruction (14) is located in the delay slot of the instruction (13), and is apparently placed after the instruction (13). However, when the branch is taken in (13), this instruction is also executed. You.

The instruction with “au” in the address invariance column in FIG. 5 means that the memory address does not change every time the loop is repeated by the load Z store instruction. This is clear from the fact that the contents of the address register are not rewritten. Also, u or ίu in the column of data invariance means that the contents of the result register of the instruction do not change as the loop proceeds. For the instruction in (5), such an assumption is made, and the others are consequent to the relation between the assumption and the delivery of the invariant data of the address.

FIG. 6 shows a stage flow of the pipeline when the instruction sequence of FIG. 5 is executed by the configuration of the present invention. In Fig. 6, the horizontal axis indicates the flow of time from left to right, and the vertical axis indicates the instruction number. Starting from the loop start in (4), the first stage flow and the second and subsequent stage flows are shown in a superimposed manner. From the second time onward, the instruction numbers are distinguished by appending “'”. The reason why the progress is accelerated in the middle after the second time is due to the use of the history information. Also, r, a, w, L, ST, i w, ia, fw, ba, and bb in FIG. 6 mean the stages shown in the description of FIG. 2, FIG. 3, and FIG. The situation is described below.

In the first progression of the loop, since there is no history information for each instruction, the V fields 1341, 1441, and 1541 in the history queue are all "0", and the stage progress is skipped. Never.

As the stage progresses, regarding the operation instructions, in the second stage, the operation input data is transmitted via lines 2201 and 3201, and in the third stage the operation result data and condition code are transmitted on lines 2302, 2303 and 3302. Written to the history storage 1 4 5, 1 5 5 via 3 303. For load / store instructions, in the fourth stage the memory address is written to history storage 145 via line 2401 and the load / store data via 2402. Condition code in the second stage for branch instructions And the destination address is written to history record 35 via line 4002. The history information is stored in the history storage 144 of the general-purpose operation unit for fixed-point operation instructions and mouth storage instructions, and in the history storage 155 of the floating-point operation unit for floating-point operation instructions. The comparison / branch instruction is written to both the general-purpose operation unit and the history memories 144 and 155 of the branch operation unit.

In addition, when executing the above instruction, the address of the instruction in the main memory is also added to the history storage, and the ladr of the stage to write the history (1 adr of any of 2 1 2, 2 1 3, 2 1 4) Is written. The timing of writing is when writing the history data to the history storage first, and when adding the history data for the instruction to the history storage, new history data is added to the line corresponding to this address. The line for writing the instruction address to the history storage is omitted from the figure.

In FIG. 6, the instruction (11) is executed before the instruction (10) because the instruction (11) is a fixed-point operation instruction and the instruction (10) is a floating-point operation. Instructions, where each instruction is executed by a separate arithmetic unit, and instruction (10) uses the execution result of instruction (9). Also, the execution of the instruction (11), which is first executed by the general-purpose arithmetic unit and then executed by the floating-point arithmetic unit, is in the middle of execution because the instruction (11) is floating-point This is because the execution result of the instruction (10) being executed by the operation unit is used.

After completing the first loop, the loop returns to instruction (4) 'and the next loop starts. In the first stage (r) of the operation instruction (4) ', regarding the general-purpose register 9, the comparator 241 a uses the history value from the history queue 144 43 and the general-purpose register 144 a. Is compared with the current value read from the. Since the contents of general-purpose register 9 have been updated with the instruction (11) after storing the history value in the previous loop, the history value and the current value do not match. Therefore, the result of the logical product 25 1 is “0”, “0” is set in the valid bit 2 12, and the instruction word 211 of the first stage is sent to the second stage 2 12, and thereafter, The normal stage operation is performed.

In the execution of the subsequent floating-point load instruction (5) ', first, in the first stage, the comparison between the history value of general-purpose register 16 and the current value is performed by comparator 241 a, and the history value and general value of general-purpose register 22 are compared. The comparison of the values is made using the comparator 241b. The current value of general register 16 is updated using the value of general register 9 in the immediately preceding instruction (4) ', and differs from the history value, so the result of the AND circuit 251 is'0', All stages are executed as in the previous instruction (4) '. In the fourth stage, the data read to 224b and the history value of the history register 234 are compared using the comparator 244a, and since both are equal, the history is stored via lines 2404 and 2003. The value of the effective field 1457 of the line of the instruction (5) is incremented by one. The data in the data register 224b is sent from the line 2402 to the floating point arithmetic unit (Fu), and is written to the floating point registers 152a and 152b via the line 3302 and the line 3001 in FIG. In the next operation instruction (6) ', the first stage compares the current value with the history value of general-purpose register 8 and the current value with the history value of general-purpose register 23. As a result of the comparison, both are equal, and the operation instruction (6) ′ is the second execution, so that the V bit 201 is “1”. The result of [Route 25] is '1', and the instruction word of the first stage instruction register 2 1 1 and the history value of the history queue skip the second stage, and the instruction word register 2 1 3 of the third stage Is transferred to the history register 233. In addition, the effective count 1457 of the line of the instruction (6) of the history storage 1450 is incremented via the lines 2105 and 2003. In the third stage, since the load stage of the preceding load instruction is in progress, after waiting for one cycle, the result register value (H data R) of the history register 2 33 is transferred to the general register 1 via lines 2 3 0 1 and 2 Writing to 42a and 142b is completed.

The operation of the following operation instructions (7) 'and (8)' is not affected by the preceding instruction, so the operation instruction (6) 'except for the operation that waits for one cycle in the middle of operation instruction (6)' Same as'. The operation of the operation instructions (7) 'and (8)' in the second loop skips the second stage compared to the operation of the operation instructions (7) and (8) in the first loop. Time is shortened.

In the floating-point load instruction (9) ', the first stage in FIG. 2 compares the current value with the history value of general-purpose register 18 and compares the current value with the history value of general-purpose register 3 1 at the first stage in FIG. A comparison is made. The result of the comparison is the same for both, and the V-bit 201 is "1" because the spoken instruction (9) 'is the second execution, and from this, the logical product circuit 25 The result of 1 is '1', and after updating the effective count 1 4 5 7 of the history record from lines 2 105 and 2003, skip the second and third stages and go to the fourth stage move on. At this time, the instruction word of the first-stage instruction register 211 and the history value of the history queue are stored in the second and third stages. It skips and moves to the instruction word register 214 and the history register 234 of the fourth stage. In the ^4th stage, the history valid bit 2 64 power by the spoken instruction; "]", the result value (H data R) of the history register 234 is read from the line 2405 to the floating-point operation unit (F u) Send to 15 In the floating-point operation unit 15 in FIG. 3, data is written to the floating-point registers 152a and 152b from lines 3302 and 3001.

The next operation instruction (1 0) 'is executed in the floating-point operation unit 15 in FIG. In the first stage (ir), the current value and the history value of the floating-point register 7 are compared by the comparator 34 1a, and the current value and the history value of the floating-point register 8 are compared by the comparator 34 1b. Are compared by Since these comparison results match each other, and because the operation instruction (1 0) ′ is the second execution, V bit 301 is “1”, so the result of the AND circuit 35 1 Becomes "1", and from the line 3 2005, the effective count 1 5 5 7 of the history memory 1 5 5 is updated, and then the second stage is skipped and proceeds to the third stage. At this time, the instruction word of the first-stage instruction register 311 and the history value of the history queue are skipped to the second stage, and are stored in the third-stage instruction register 313 and the history register 333. Moved. In the third stage, since the history valid bit 3 6 3 is “”, the result value (Hdata R) of the history register 3333 is transferred to the floating-point register 1 5 2 via lines 3 301 and 300 1. a,] 5 2 b.

The operation instruction (1 1) 'is executed by the general-purpose operation unit 14. Every time the contents of input register 9 are counted up and the current value and the history value are not equal, Stage is executed.

The floating-point store instruction (] 2) 'is implemented in the general-purpose arithmetic unit 14. At the stage (r), the current value of the general-purpose register 26 is compared with the history value, and the current value and the history value of the general-purpose register 20 are compared. since V bit is "1", the aND circuit 2 5 1 outputs "1" and becomes _c result, it updates the valid count field 1 4 5 7 history storage 1 4 5, the second scan Skip the stage and proceed to the third stage (ir). At this time, the instruction word of the instruction register 2 11 of the first stage and the history value of the history queue 1 4 4 skip the second stage, and the instruction word register 2 13 of the third stage. Moved to history register 2 3 3. In the third stage (ί r), the floating-point operation unit 13 reads out the store data value of the floating-point register 13 via the line 3106 of the floating-point operation unit, and sets it in the data register 222b of the general-purpose operation unit. I do. In the following fourth stage, the store data of the data register 224b and the history store data (H data R) in the history register 234 are compared by the comparator 244a. Update the valid count field 1457 of the history storage 1405 via 404, line 2003. Also, the data store operation is suppressed through the circuit 254. On the other hand, if the comparison results of the comparators 244a do not match, the store operation is performed because the previous store data and the current store data are different. In addition, in order to cope with the destruction of the history information due to the execution of the store operation of the store instruction, the address information (HAdr) of the history register 234 is stored in the history storage 1 via lines 2406 and 2002. 4 5 and the invalidation field of the row with the same value as HA dr in the data address field 1 4 5 6 Set the field 1 4 58 to "1" to invalidate the line.

Since the following instruction (1 3) 'is a comparison / branch instruction, the general-purpose operation unit 14 and the branch operation unit 13 cooperate to execute the instruction (1 3)'. In the first stage of the general-purpose arithmetic unit 4, compare the current value of general-purpose register 9 with the history value, and compare the current value of general-purpose register 11 with the history value. Since the current value of general-purpose register 9 is different from the history value, normal stage progress is performed. In the second stage, the comparison operation is performed by the fixed-point operation circuit 146, and the condition code (CC) of the comparison result is set in the register 242. In the third stage, the condition code of the register 242 is written from the lines 2303 and 2002 to the condition code field 1452 of the history storage 1450, and is also sent to the branch operation unit (Bu) 13 at the same time. In the branch operation unit shown in FIG. 4, in the second stage (ba), the condition code is received in the register 441, and this is compared with the mask field of the instruction word 4 1 1 by the comparator 4 5 1. The presence / absence of the obtained branch is determined by the information 442 indicating the presence / absence of the branch, and the condition code (HCC) of the history register 43 1 is compared by the comparator 471 with the condition code (HCC) of the history register 431. " In the following second stage (b b), the effective count field 1 354 of the history storage 1 35 is updated from the line 4 403, and the process branches to the beginning of the norape.

The instruction (14) 'in the delay slot is a fixed-point load instruction. In the first stage of Fig. 2, the current value of general-purpose register 30 is compared with the history value, and since they are equal, the effective count field 1457 of the history storage 145 is updated from lines 210 and 2003, and the second and third stages are updated. Skip the fourth step Proceed to In the fourth stage, the result data (HDa \ aR) of the history register 234 is written to the general-purpose registers 140a and 144b from lines 2403 and 2001. Thus, as shown by the thick line in FIG. 6, in the second and subsequent loops, the instruction sequence can be executed earlier than the first loop by skipping the stage using the history data. If there is no free space at the time of new writing to the history storage, the free space is deleted in order from the one with the smallest effective count to create a free space. This is to control so that the history of the instruction of the address whose history record was valid as much as possible remains in the history memory. Instructions with no history at the time of execution are the V fields 1341, 14441, and 1541 of the history queue; "0"; in this case, they are executed without skipping the stage and the history information is Registered in history memory.

In the history storage, reading and writing are performed simultaneously from the register section of the instruction queue and each stage of instruction execution.However, depending on the instruction address, the number of instruction stages + 1 (5 in this example) bank is stored. By dividing and configuring, access concentration can be prevented.

If there is a store from another processor to the shared storage area, such as when a multiprocessor is formed, the data address of the history storage is stored in the same way as the store from the own processor. Invalidate the row having the data address 1456, which matches the address. If the storage address is unknown, invalidate all lines related to the load store in the history storage.

Also, in FIG. 1, the history records are distributed and arranged in each operation unit. However, like the history cache (history storage) 17 in FIG. Instruction cache] You may have it corresponding to the instruction on 1. In this case, the management of the replacement of the history information stored in the history storage (registration of the history data in the history storage or deletion of the history information from the history storage, etc.) is performed together with the instruction cache. The history information is temporarily taken into the history buffer (HBUF) 122 at the same time as the instruction sequence is taken into the instruction buffer (I BUF) 122 of the instruction control unit 12, and the history queue of each operation unit is taken. — Distributed to 134 (HQB), 144 (HQG) and 154 (HQF). The history information updated as a result of the instruction execution is returned from the output history queues 137 (HQB), 147 (HQGO) and 157 (HQFO) to the history storage 17 via the history buffer (HBUF) 122. It is.

The present invention is not limited to the format of the instruction sequence shown in FIG. Any form of instruction that can specify input registers, address registers, result registers, and direct values can be used. Alternatively, it may be in the form of a command word that specifies a plurality of operations with a single command, such as a VLIW (VeryLargeInstruckintiornWord) computer.

Figure 1 shows an example of three arithmetic units, but this may be more or less. In addition, since it is the essence of the invention to skip the execution of a part of the stage by associating the history information with each instruction, each unit has a plurality of instruction queues or multiple instruction queues such as a multi-pipeline computer and a superscalar computer. It can be applied to a configuration with an arithmetic unit.

According to the present invention, as shown in FIG. 6, the number of pipeline stages required to execute each instruction can be reduced, and as a result, the execution time of an instruction sequence can be reduced. Also, Since unnecessary load restore operations on the memory are suppressed, the load of storage management such as cache control and address conversion can be reduced, and as a result, the average execution time of the cache store instruction can be reduced. Furthermore, since the instruction history is used when the instruction address in the main memory matches, the history information is reused at a high rate and the history information can be used effectively. Industrial applicability

As described above, the instruction processing device according to the present invention is useful for an instruction device that reads an instruction from a storage device by specifying an address and executes the instruction, and specifies an input register, an address register, a result register, a direct value, and the like. It is suitable for application to an instruction processing device that processes available instructions.

Claims

The scope of the claims '

1. An instruction processing device for processing an instruction specified by an address, wherein when executing the instruction, the content of the data processed by the instruction and the address of the instruction are stored as history information in pairs. A history storage device, recording means for recording the history information in the history storage device when executing the command, and contents of the history information stored in the history storage device when the command of the same address is executed again. Re-executing means for executing the instruction by using the same, and updating means for updating the contents of the history information stored in the history storage device when re-executing the instruction of the same address. Instruction processing unit.

2. If the instruction is an operation instruction, the data includes data to be input for the operation and data of the operation result, and the re-executing means includes: data to be input to the operation of the operation instruction at the present time; A comparator for comparing the data input to the operation of the operation instruction recorded in the history storage device, and a data of the operation result recorded in the history storage device when the comparator indicates a match. 2. The instruction processing apparatus according to claim 1, further comprising: means for obtaining operation result data of the operation instruction at the present time.

3. If the instruction is a store instruction, the data includes a store address accessed by the store instruction and store data, and the re-executing means stores the store address of the store instruction at the present time and the history storage device. A first comparator for comparing the store instruction address of the store instruction stored in the history instruction with the store data of the store instruction at the present time and the store instruction of the store instruction stored in the history storage device. A second comparator for comparing with the first comparator, and means for inhibiting the store operation of the store instruction at the present time when the first comparator and the second comparator both indicate a match. The instruction processing device according to claim 1, wherein

4. The re-executing means includes means for executing a store instruction at the present time when the first comparator and the second comparator do not indicate a match, and in this case, the updating means 2. The instruction processing device according to claim 1, wherein said data invalidates said data in said history storage device having said store destination address.

5. When the instruction is a store instruction, the data includes the contents of a group of address registers forming a store address and a store address, and the re-executing means includes the current address register. Comparing means for comparing the contents of the group with the contents of the address register group recorded in the history storage device; and when the comparing means indicates a match, the calculation of the storage destination address is suppressed and the history storage address is suppressed. 2. The instruction processing device according to claim 1, further comprising means for using a storage destination address recorded in the device.

6. The re-executing means has means for executing a store instruction at the present time when the comparing means does not show a match, and in this case, the updating means has the store destination address having the store destination address. 6. The instruction processing device according to claim 5, wherein the data of the device is invalidated.

7. If the instruction is a load instruction, the data includes a load source address accessed by the load instruction and load data, and the re-executing means includes a load source address of the load instruction and a history storage at the present time. A first comparator for comparing a load source address of the code instruction recorded in the device with the first comparator; 2. The instruction processing apparatus according to claim 1, further comprising: means for converting the load data recorded in the history storage device into a piece of port data by executing a port command at the current time when a match is found.

8. If the instruction is a load instruction, the data includes load data and the contents of an address register group forming a load source address, and the re-executing means executes the load instruction at the present time. A comparing means for comparing the content of the address register group with the content of the address register group of the load instruction recorded in the history storage device; and 2. The instruction processing device according to claim 1, further comprising means for using the recorded load data as load data of a result of a load operation of a currently loaded instruction.

9. The history information recorded in the history storage device has a counter for counting the number of times the re-executing unit has executed the instruction using the history information, and the updating unit includes: Means for updating the counter when an instruction is executed using information, and means for deleting the history information in ascending order of the counter value when the storage area of the history storage device is insufficient. 2. The instruction processing device according to claim 1.

10. The instruction processing device executes the instruction without using history when there is no history information related to the instruction in the history storage device when executing the instruction, and newly stores the history information related to the instruction in the history storage device. 10. The instruction processing device according to claim 9, wherein the instruction processing device is registered with a computer.