JPS6284340A - Data processor - Google Patents

Abstract

PURPOSE:To shorten time for processing by starting the processing of succeeding instructions stopped at the time of occurrence of register conflict by using information outputted by an associative memory. CONSTITUTION:An instruction memory device 304 and an operand memory device 326 are addressed by the address of 24 bits in a byte unit. The prereading of the instruction is made in the unit of 4 instruction words that start from 4 instruction word boundary on an instruction memory device 302 at all times. An address adder 24 adds the content of a register designated by X2 field of the instruction word. The result of operation of preceding instruction at the time of preceding execution or memory operand of preceding instruction is stored in an associative memory device 320, and when the occurrence of register conflict is detected by a register conflict detecting device 322, the associative memory device 320 is retrieved. The result of operation of preceding instruction that causes register conflict is obtained by using information stored in the associative memory device 320.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing device, and particularly to speeding up an information processing device using pipeline control.

[Background of the invention]

In a pipeline-controlled information processing device, the entire instruction processing is divided into a plurality of partial processes, and an independent processing device is provided for each partial process. First, a first instruction is processed by a processing device that performs a first partial process.

When the processing is completed and the processing moves to the processing device that performs the second partial processing, the processing device that performs the first partial processing starts processing the second instruction. When the first instruction is transferred to the processing device that performs the third partial processing, the second instruction is processed by the processing device that performs the second partial processing, and the third instruction is processed by the first partial processing device. In this way, execution of instructions subsequent to the first instruction is started before the entire processing of the first instruction is completed, so that high instruction processing performance can be achieved in an information processing device using pipeline control.

However, if an instruction (hereinafter referred to as the preceding instruction) that precedes a certain instruction (hereinafter referred to as the subsequent instruction) modifies a certain register, and the subsequent instruction is an instruction that references that register (register conflict occurs). called the stratum corneum,
), instruction processing does not proceed as described above. That is,
Until the preceding instruction writes the operation result to the register or until the preceding instruction generates the operation result, the entire processing of the subsequent instruction, at least the partial processing that refers to the register, must be stopped. Suspension of execution of subsequent instructions due to such a registration conflict is a major impediment to performance improvement in pipeline-controlled information processing devices.

An example of shortening execution stoppage due to register conflict is JP-A-58-96346.

[Purpose of the invention]

An object of the present invention is to provide a pipeline-controlled information processing device that eliminates the suspension of execution of subsequent instructions when a register conflict occurs and has high instruction processing performance.

[Summary of the invention]

In the present invention, when a subsequent instruction is executed using an operation result written to a register by a preceding instruction, the processing of the subsequent instruction that uses the operation result is stopped until the operation result is finalized. In a data processing device, the instruction address of the preceding instruction or -, the instruction address of the instruction before the preceding instruction, the pre-read address when pre-fetching the preceding instruction, the pre-reading address when pre-reading the instruction before the preceding instruction The memory operand address of the preceding instruction, the operation result, and the operation result in correspondence with an associative key consisting of all or each arbitrary bit position data and the memory operand address determination information of the preceding instruction. means for storing information indicating that the store instruction is executed by the data processing device, and searching for whether or not the memory operand address that matches the store address of the store instruction exists in the storage means when the store instruction is executed by the data processing device. In some cases, the corresponding operation result is stored in the store instruction.
associative writing means for rewriting the information indicating that the operation result is a memory operand by rewriting the information with data; When the associative key is stored, a means for outputting the corresponding operation result or the memory operand, and when the output means outputs the operation result, the output means outputs the operation result. If the operation result from the output means is equal to the operation result obtained by the operation of the preceding instruction, the processing of the subsequent instruction that has been started is started using the operation result of the preceding instruction. means for continuing the processing and, if not equal to 1, invalidating the processing of the subsequent instruction and re-executing the processing of the subsequent instruction using the operation result obtained by the operation of the preceding instruction; - When an operand is output, the method is characterized by having means for performing an operation specified by the preceding instruction on the memory operand and using the result of the operation to start processing of the stopped subsequent instruction. We propose a data processing device that

Thereby, the processing of a subsequent instruction that is stopped when a register conflict occurs can be started using the information output from the associative memory, so that the above object can be achieved.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, the instruction format used in this embodiment will be explained using FIG. 1A. In this instruction format, each instruction word has a length of 4 bytes. The first byte represents the operation code (Op), the upper 4 bits of the 2nd and 3rd bytes represent the three register instruction fields (R1, X2.B2), the lower 4 bits of the 3rd byte and the 4th byte represent the displacement (B2).

In this instruction format, each register designation field is 4 bits each and each designates one of the 15 registers.

If the instruction is other than the 5tore instruction, this meaning is
The sum of the contents of the general-purpose register pointed to by field B2, the contents of the general-purpose register pointed to by field B2, and displacement D2 is taken as an operand address, and the contents of the location in the main memory pointed to by this address (referred to as the second operand), and R
The operation is to perform the operation indicated by the operation code Op on the contents of the general-purpose register indicated by field 1 (referred to as the first operand) and store it in the general-purpose register indicated by field R1.

When the instruction is a store instruction, contrary to the above, the contents of the general-purpose register, which is the first operand, are stored in the location on the main memory, which is the second operand.

Note that this instruction format is based on the IBM system (Systsm).
/370 instruction format, and for more details, see "IBM System Stem" /370 Operation Processing (370 Principles of 0per
ation)”.

FIG. 1B is a mnemonic representation of the command shown in FIG. 1A.

FIG. 2 is an example of an instruction sequence that causes a register conflict. The preceding instruction (■) is an Add instruction, which means that the contents of the address obtained by adding the contents of register 1, contents of register 2, and displacement 100 are added to the contents of register 5, and the result is stored in register 5. . Subsequent instruction (■)
is a Substruct instruction, and the contents of register 1, the contents of register 5, and the displacement 150
This means that the contents of the address obtained by adding the above are subtracted from the contents of register 8 and stored in register 8.

Since the preceding instruction writes the operation result to register 5, and the subsequent instruction uses the contents of register 5, a register conflict occurs.

Next, an overview of the overall configuration of the embodiment will be explained using FIGS. 3A and 3B. Figures 3A and 3B.

When combined, it becomes an overall configuration diagram of the embodiment. In this embodiment, as the operation result of the preceding instruction, the operation result of the previous execution of the preceding instruction stored in the associative memory or the result of performing an operation on the second operand of the preceding instruction stored in the associative memory is used. It is.

First, 304 is an instruction storage device, and 326 is an operand storage device. Instruction storage 304 and operand storage are addressed with 24-bit addresses in bytes.

100 is a prefetch instruction address register.

Prefetching of instructions is always performed in units of four instruction words starting from a four instruction word boundary on the instruction storage device. Therefore, the prefetch instruction address register (IFA) 100 stores the upper 20 bits (bits 0-19) of the 24-bit address.

102 is a delay register of the prefetch instruction address register.

104, 106, 108, 110 are instruction buffers IBO, I, IB2. IB3, and the four instruction words read ahead from the instruction storage device 304 are stored in this order.

112 is an instruction register, and 114 is an instruction counter. One instruction word consists of 4 points from the instruction word boundary on the instruction storage device.
Always placed in the byte. Therefore, the value of the 6-instruction counter 114, in which the upper 22 bits (bits 0-21) of the 24-bit address are stored, is:
This is the instruction address of the instruction word in the instruction register 112 at that time.

118 is a register file consisting of 16 registers.

324 is an address adder, and the content of the register indicated by the X2 field of the instruction word, that is, the X2 register value, and the content of the register indicated by the B2 field, that is,
Add B2 register value and displacement D2. The addition result is stored in operand address register 120.

122 is an operand data register, and 330 is an A
It is LU.

124. 130, 132, 134, and 136 are the delay register of the instruction register 122 and the instruction counter 114, respectively.
delay register of X2 register value delay register of B2
Delay register value of register value and delay register of prefetch instruction address, operand address register 1
When the operand address is stored in 20, the instruction register value, instruction counter value, X2 register value,
The B2 register value and the prefetch instruction address at the time of prefetching the instruction are stored.

126. 138, 140, 142, 144 are delay registers of registers 124, 130, 132, 134, 136, respectively, and when operand data is stored in the operand data register 122, the instruction register value and instruction counter value of the instruction are , the X2 register value, the B2 register value, and the prefetch instruction address at the time of prefetching the instruction.

320 is a content addressable memory device, and 322 is a register conflict detection device.

Next, the overall operation in the case where there is no register conflict will be described using the overall configuration diagrams in FIGS. 3A and 3B and the timing chart diagram in FIG. 5.

As shown in FIG. 5, it is assumed that the prefetch address for prefetching the first to fourth instructions is stored in the prefetch address register from time TO. Further, it is assumed that the instruction register 112 and the instruction counter 114 store the instruction before the first instruction, that is, the instruction word and instruction address of the O-th instruction before time T2. Look-ahead address register 100
The address of the instruction memory bag fi! is transmitted via signal l1500.
304, and four instruction words starting from that address are output to the signal line 506, and the four instruction words from the first instruction word to the fourth instruction word are sent to the instruction buffers 104 and 106 at time T1.
, 108, 110 6 address incrementer 302
inputs the address of the look-ahead address register 100 and outputs an address incremented by four instruction words to the signal line 502. The signal on the signal line 586, which is the selection signal of the selector 300, is normally a "right selection signal" (
(The only time it takes a value other than the "right selection signal" is as explained below). At this time, the signal on the signal line 502 passes through the selector 300 and is output to the signal line 50B, is stored in The stored time is time T4, which is four cycles after time TO. instruction buffer 10
These four instruction words are stored at 4,106°108.110 until time T5 when the next four instruction words are stored. The preread address register 100 is normally increased by four instruction words in this way, so the instruction buffer 104゜106.108
, 110, subsequent instructions are read ahead in units of four instructions and stored in sequence.

Before time T2, the instruction counter 114 has the Oth
The instruction address of the instruction was stored.

The value of instruction counter 114 is applied to address incrementer 310 via signal 8530 and is incremented by one instruction word.
This is the instruction address of the first instruction. The increased value is input to selector 308 via signal line 520. The selection signal 586 of the selector 308 is normally the "right selection signal" as described above, and at this time, the value of the signal line 520 is the same as that of the selector 3.
08 to the signal line 518. Signal line 518
The value of is stored in the instruction counter 114. The value is also applied to selector 306. The selector 306 looks at the lower two bits of the 22-bit address value on the signal line 518, and if it is 0, the data on the signal line 508 is a signal.
If it is 1, the data on signal line 510 is output to signal line 516. If it is 2, the data of the signal 1l1512 is output to the signal 516,
If it is 3, the data on signal line 514 is output to signal 8516. As a result, at time 0 T2 when the contents of the instruction buffer next to the instruction buffer set at the time before the instruction register are selected by the selector 306 and stored in the instruction register 112, the first instruction is transferred from the instruction buffer IB○ 104. The instruction address of the first instruction is stored in the instruction register 112 and the instruction address of the first instruction is simultaneously stored in the instruction counter 114.

Further, the value of the prefetch instruction address register is stored in the IFASV register 102 at time T2, which is two cycles behind the prefetch instruction address register IFALOO.

16 to the selectors 312 and 314 via the signal line 532.
The values of a register file 118 consisting of registers are applied. Furthermore, four bits of the X2 field of the first instruction in the instruction register 112 are applied to the selector 312 via a signal line 524. This causes the selector 312 to
Signal the value of the register indicated by the 2 field, 1X53
Output to 4. Four bits of 82 fields of the first instruction in the instruction register 112 are applied to the selector 314 via a signal line 526. This causes the selector 314 to
The value of the register indicated by field 2 is output to the signal line 536. Normally, "0" is applied to the signal lines 592, 590, 593, and 591.

([Values other than OJ are applied only in the case explained below.) At this time, the selector 31 shown in FIG.
According to the operation diagram of No. 6,318, the value of signal line 534 is outputted to signal line 540 via selector 316,
The value of 36 is output via selector 318 to signal $542.

In this way, the contents of the register indicated by the X2 field of the first instruction are input to the address adder via the signal line 540, and the contents of the register indicated by the B2 field of the first instruction are input via the signal line 542. is input. Furthermore, the displacement D2 of the first instruction in the instruction register 112 is input via the signal line 528. The address adder adds the above three input values and outputs the operand address of the first instruction, which is the addition result, to the signal line 548, which is stored in the operand address register 0A120 at time T3.

At the same time, the first instruction word is stored in the IRI register 124 via the signal line 522, and the ICI register 130
The first instruction address is stored in the GRXI register 132 via the signal line 530, the X2 register value of the first instruction is stored in the GRXI register 132 via the signal line 540, and the first
The 82 register value of the instruction is stored via the signal line 542, and the IPAI register 136 stores the prefetch instruction address when the first instruction is prefetched.

The operand address of the first instruction in the operand address register 120 is applied to the operand storage device 326 via a signal line 550, and the operand data of the first instruction at the location indicated by the address is outputted to the signal line 552. Ru.

At time T4, the operand data of this first instruction is stored in the operand data register 122.

At the same time, the IRIR1 register first instruction word is stored in the IR2 register 126 via the signal line 562, and the IC
The instruction address of the first instruction is stored in the second register 138 from the ICI register 130 via the signal line 572,
GR via GRX2R1 register 140 signal line 570
The x2 register value of the XIR1 register 1321 instruction is stored, the 82 register value of the first instruction is stored from the GRB raster 134 via the GRB2R1 register 142 signal line 568, and the IFAI The prefetch instruction address when the first instruction word is prefetched is stored in the register 136, and the operand address is stored in the OA2 register 706 from the OA register 120 via the signal line 550.

ALU 330 has three input signal lines. signal line 55
4, the first
The operation code of the first instruction in the IR2 register 126 is input from a signal line 594 to which operand data of the instruction is input. The value of the register file 118 consisting of 16 registers is applied to the selector 328 via a signal line 532, and the value of the R of the first instruction is applied via a signal line 558.
1 field is applied. As a result, the selector 32
8 applies the value of the register indicated by the R1 field, ie, the R1 register value, to signal line 560, which is input to ALU 330. ALU is signal line 56
The input data from signal line 554 is used as the first operand data, and the input data from the signal line 554 is used as the second operand data. The operation code indicated by 594 is calculated, and the result of the calculation is output to the signal line 556.

The calculation result of the first instruction is applied to the register file 118 via a signal line 556, and the I/O signal is applied via a signal line 558.
At time T5 when the R1 field of the first instruction in the R2 register 126 is applied, the operation result of the first instruction is transferred to the register indicated by the R1 field, that is, R1.
written to a register.

Note that when the instruction is a store instruction,
This fact is detected by a store command detector 710 and sent to the operand storage device 3 via a signal line 712.
26. As a result, the operand storage device stores data input via the signal line 708.
The contents of the R1 register of the store instruction input via the signal tile 560 to the operand address of the instruction are written at time T5. Note that writing to the R1 register described above is not performed at this time.

With the above steps, the processing of the first instruction is completed.

In the processing of the second instruction, first, at time T3, the second instruction word is stored in the instruction register 112, and the instruction address of the second instruction is stored in the instruction counter IC. Thereafter, the processing proceeds in the same way as the first instruction.

The processing of the third and subsequent commands is performed at a time one cycle behind the processing of the previous command. Proceed as per the second command.

However, since instruction prefetching is performed in units of four instruction words, prefetching instruction address register Zoo, instruction buffer 104.
106, 108, 110. Storing to the IFASV register 102 is performed once every four cycles.

As mentioned above, if there is no register conflict, 1
Instruction processing progresses in each cycle.

Next, we will move on to an explanation of the overall operation when there is a register conflict, but before that, we will explain the content addressable memory device 3 using FIG.
Explain 20.

The storage capacity of the associative memory device in this embodiment is 10 words.

Each word is divided into an IC storage section ICP346 and an IR storage section IR.
P348 and X2 register value storage unit GRXP350 and B2
Register value storage unit GRBP 352, prefetch instruction address storage unit IFAP 354, and data storage unit DATAP
356, an address storage section ADDRP 345, and a flag storage section FLGP 347.

Applying data to signal lines 530, 522, 540, 542, 500 causes the content addressable memory to search. signal line 5
30,522,540,542゜500 data and I
C storage unit ICP346° IR storage unit IRP348. X2
Register value storage unit GRXP350. B2L/Jister value storage unit GRBP352.

When there is a word whose data in the prefetch instruction address storage unit IFAP354 all match, the match detector 3
44 outputs "1" and sets the HITL register 156 to "1".
” and the data storage unit DATAP 3 of that word.
56 data is stored in the DATAL register 15g,
The data in the flag storage unit FLGP 347 is stored in the FLGL register 157. When there is no matching word, match detector 344 outputs an "O" and causes IITLL/Jitter 156 to rOJ k-.

Meanwhile, signal-jt, m584 to rl' or signal Al5s6
When ``0'' is applied to
08 respectively to the IC storage unit ICP346. I
R storage unit IRP348. X2L/Jister value storage unit GRX
P350. B2 register value storage unit GRBP352, prefetch instruction address storage unit IFAP354, data storage unit DATAP 356 address storage unit ADDRP 345
data, and register the word "rl" in the flag storage unit FLGP347. At that time, the IC storage unit ICP34
6. IR storage unit IRP34g.

X2 register value storage unit GRXP350. B2 register value storage unit GRBP352, prefetch instruction address storage unit I
If a word that matches all of the FAP 354 data is already stored, it is overwritten on top of that word. If a matching word is not yet stored, a new word is assigned and registered.

Further, when “1” is applied to the signal line 712, that is, when a store instruction is executed, the associative memory device receives the store instruction sent via the signal line 708.
ore) detects whether a word exists whose operand address of the instruction and the address store ADDRP match, and if so, stores the data store DATAP of all such words to the store ( Rewrite with the contents of the R1 register of the Store) instruction,
In addition, "0" is stored in the flag storage unit FLGP of that word.

Note that "1" in the flag storage unit FLGP means that the calculation result when the instruction was previously executed is stored in the corresponding data storage unit DATAP.
“0” in GP means that the second operand data is stored in the corresponding data storage unit DATAP.

This concludes the explanation of the associative memory device.

Next, the operation when there is a register conflict will be explained. The two instructions in FIG. 2 are considered as instructions with a register conflict, and the Add instruction is assumed to be the first instruction, and the Subthrust instruction is assumed to be the second instruction. The third and subsequent instructions are any instructions that do not cause a register conflict with these instructions.

In the present invention, the operation result of the preceding instruction (in the example considered below, the first instruction) causing the register conflict is obtained using information stored in the content addressable memory device. Therefore, when executing a preceding instruction, whether prediction is possible or not is determined by whether or not there is information in the associative memory.

First, a case will be described in which there is no information about previous execution in the associative memory. FIG. 6 is used as a timing chart.

Most of the instruction prefetching from the first instruction to the fourth instruction and the processing of the first instruction are the same as those in the case where there is no register conflict as described above. That is, in the timing chart of FIG. 6, IFA for the first to fourth instructions, IBO to 3° IFASV, IR/IC, OA/IRI/ICI/GRXI/GRB for the first instruction.
I/IFAI.

OD'/IR2/IC2/GRX2/GRB2/IFA
2. The timing of the OR is the same as in FIG.

The other parts will be explained below.

First, read ahead instruction address register 100 from time 1 TO.
The prefetch instruction address stored in the signal, [500
The prefetch instruction address storage unit IF of the associative memory device via
It is applied to AP354. Also, at time T2, the instruction word of the first instruction, the instruction address, the X2 register value, B
2 register values are signals 8522, 530, 540 respectively
, 642 respectively to the IR storage section 3 of the associative memory device.
48° IC storage section 346. X2 register value storage section 350
It is applied to the °B2 register value storage section 352.

The associative memory device is connected to the signal lines 530, 522゜540.5.
Search using 42,500 pieces of data.

Now, we are considering the case where there is no information about the previous execution in the associative memory, so at time T3, the HITL register 1
rOJ is stored in 56. Furthermore, this “0” is applied to signal line 546.

At time T3, the instruction word of the first instruction, Add instruction, is stored in the IRI register 124, and the instruction word of the second instruction, 311) gtract instruction, is stored in the instruction register 112. Therefore, signal! 582
"5" in the R1 field of the first instruction is applied to the top,
The X2 field "5" of the second command is applied to the signal line 542. Since it is assumed that there is no register conflict except for the first and second instructions, the signal lines 558 and 52
A value different from "5" is applied to 6. Therefore, the output of the minus number comparison circuit 160 becomes "1", and the output of the other coincidence comparison circuits 162, 164, and 166 becomes rOJ. Therefore, the output signal line 593 of the OR circuit 168 becomes "1", and the output signal llA391. of the OR circuit 170 becomes "1".
Output signal line 592 of AND circuit 172. AND circuit 17
4 output signal line 590. The output signal line 584 of the AND circuit 180 becomes rOJ.

Since the signal line 592 is rOJ and the signal line 593 is "1", no significant data is output on the signal line 540, as shown in FIG. The 82 register value of the second instruction is transferred to signal line 5.
42 to address adder 324. From signal line 528, the displacement of the second instruction is applied to the address adder.

As a result, no significant data is stored in the operand address register 120 at time T4.

Also, the IRI register 124. ICI register 130,
No significant data is stored in the GRXIL/13 register GRBIL/13 register IFAI register 136 either.

In the subsequent operation of the second instruction, no significant data is output on the signal line 540, so the address adder 548 does not output any significant data. Therefore, even at time T4, there is no significant data in the operand address register 120. No data is stored in IRI register 124. ICI
Register 130°GRXIL/Register 13ras GRBI
No significant data is stored in the L/J, 1134° IFAI register 136 either.

On the other hand, at time T4, the first
The command word of the Add command, which is a command, is stored. At this time, the output of the minus number comparison circuit 164 becomes "1", and the output of the other coincidence comparison circuits 160°162.166 becomes "o".
Therefore, the output signal line 593 of the OR circuit 168 and A
The output signal line 584 of the ND circuit 180 becomes "1", and the output signal line 591 of the OR circuits 170 and 182 becomes "1".
6 and the output signal line 592.5 of AND circuits 172 and 174
90 becomes rOJ. At this time as well, the signal line 592 is "O" and the signal line 593 is "1", so no data is output on the signal line 540. Since no significant data is output on the signal line 540, the address adder 548 does not output any significant data, therefore no significant data is stored in the operand address register 120 even at time T5. GRXI register 132°GRB raster 134. No significant data is stored in IFA register 136 either.

On the other hand, at time T5, no significant data is stored in the IR2 register 138. At this time, the outputs of the coincidence comparison circuits 160, 162, 164, 166 are "0", so the signal lines 590, 591, 592, 593, 58
All 4,596 are "0".

As a result, the selector 316 applies the x2 register value of the second address on the signal line 534 to the address adder 324 via the signal line 540, and the selector 318 applies the x2 register value of the second address on the signal line 534 to the address adder 324.
82 register value of the second address on 6 from the signal 542
to the address adder 324 via the address adder 324. Signal line 52
From 8 onwards, the displacement of the second address is applied to the address adder.

As a result, the operand address of the second address is stored in the operand address register 120 at time T6.

Also, the IRI register 124. ICI register 130,
GRXI register 132. GRBI register 134. I
The same data as the operation when there is no register conflict is stored in the FAI register 136 at time T6.

Subsequent operations at the second address proceed in the same manner as in the case where there is no register conflict.

The calculation of the first address is performed in the ALU 330 from time T4, and the result of the calculation is applied to the content addressable memory device via the signal line 556 between times T4 and T5.

Additionally, a "1" on signal line 584 is applied to the content addressable memory. As a result, the IC storage section 346 of the associative memory device.
IR storage section 348. X2L/Jister value storage section 350. B
2 register value storage unit 352° prefetch instruction address storage unit 354. The data storage section 356 and the address storage section 347 respectively store the instruction address of the first instruction on the signal line 580, the first instruction word on the signal line 564, the X2 register value of the first instruction on the signal line 578, and the X2 register value of the first instruction on the signal line 576. 82 register value of the first instruction, the prefetch instruction address when prefetching the first instruction on the signal line 574, the operation result of the first instruction on the signal line 556, and the operand address of the first instruction on the signal line 708. , the word whose flag storage unit 347 is “1” is at time T
Registered in 5.

This concludes the explanation of the case where there is no information in the associative memory device.

Next, a case where information exists in associative memory will be explained. The associative memory may store the operation result of the preceding instruction during previous execution, or may store the memory operand of the preceding instruction.

First, a case will be described in which the associative memory device contains information results from previous executions. FIG. 7 is used as a timing chart.

The result of an operation is obtained by performing an operation on the first operand and second operand (memory operand) in an operation instruction other than a load instruction. The first operand of the previous execution may not match the first operand of the next execution, so the operation result in the associative memory is not necessarily correct.Therefore, in the following cases, the associative memory Processing of the second instruction is started with the operation result of the first instruction, and when the operation result of the first instruction is obtained later, it is compared with the operation result of the associative memory, and if there is a discrepancy, the processing of the second instruction is restarted. There is.

Most of the instruction prefetching from the first instruction to the fourth instruction and the processing of the first instruction are the same as those in the case where there is no register conflict as described above. That is, in the timing chart of FIG. 7, IFA regarding the first to fourth instructions, IBO to IFASV, I
R/IC, OA/IRI/ICI/GRXI/GRBI
/IFA1゜○D/IR2/IC2/GRX2/GRB
2/IFA2. The timing of GR is the same as in FIG. The other parts will be explained below.

First, from time To, the prefetch instruction address register 100
The prefetch instruction address stored in the signal line 500
The prefetch instruction address storage unit IF of the associative memory device via
applied to AP 354. Also, at time T2, the instruction word of the first instruction, the instruction address X2 register value, B
Two register values are connected to signal lines 522, 530, and 540, respectively.
, 542 respectively to the IR storage section 3 of the associative memory device.
48°ICE storage section 346. X2L/Jister value storage section 35
0°B2 is applied to the register value storage section 352.

The content addressable memory device includes the signal lines 530, 522, 540, .
Search using 542,500 data.

We are now considering a case where the associative memory has information from the previous execution, so at time T3, the previous operation result of the first instruction is stored in the DATAL register 158, and the FL
“1” is stored in the GL register 157, and “1” is stored in the HITL register 156. Furthermore, this “1
” is a signal! 546.

At time T3, the instruction word of the first instruction, Add instruction, is stored in the IRI register 24, and the instruction word of the second instruction, 5ubstract instruction, is stored in the instruction register 12. Therefore, the R1 field "5" of the first instruction is applied to the signal line 582, and the X2 field "5" of the second instruction is applied to the signal line 524. Since it is assumed that there is no register conflict except for the first and second instructions, the signal lines 558 and 526
A value different from "5" is applied to . Therefore, the output of the minus number comparison circuit 160 becomes "1", and the outputs of the other coincidence comparison circuits 162, 164, and 166 become rOJ. Therefore, the output signal line 593 of the OR circuit 168 and the OR circuit 1
The output signal line 596 of 82 and the output signal line 172 of the AND circuit 172 become "1". Also, the output signal line 591 of the OR circuit and the output signal line 590 of the AND circuit 174. AN
The output signal line of the D circuit 180 becomes rOJ.

The signal line 596 is a set signal for the IC5V register 58, and since this signal line is "1", the instruction address of the second instruction is stored in the IC3V register 116 at time T4, and the instruction address before the first instruction is stored in the posv register 154. The result of the calculation is stored.

Since the signal line 592 is "1" and the signal line 714 is "1", the selector 316 selects the signal line 5 as shown in FIG.
The selector 318 applies the B2 register value of the second instruction on signal line 536 to the address adder 324 via signal line 540.
42 to address adder 324. From signal line 528, the displacement of the second instruction is applied to the address adder. As a result, the operand address of the second instruction is stored in the operand address register 120 at time T4.

Also, IRI register 124. ICI register 130,
GRXI register 132. GRBI register 134. I
The same data as the operation when there is no register conflict is stored in the FAI register 136 at time T4.

The subsequent operation of the second instruction proceeds in the same manner as in the case where there is no register conflict.

The calculation of the first instruction is being performed in the ALU 330 from time T4, and the calculation result is applied to the comparator 332 via the signal line 556 between times T4 and T5. Comparator 33
The previous operation result of the first instruction stored in the DATASV register 154 is applied to the other input of No. 2.

The following operation is divided into two types depending on whether or not the calculation result in the ALU 330 matches the previous calculation result.

First, the case where they match will be explained. In this case, the signal line 58
6 is applied with "1". This "1" is selector 3
00 and 308. At this time, the selector 300 outputs the data on the signal line 502 to the signal line 506, and the selector 308 outputs the data on the signal line 520 to the signal line 518. This is the same operation as when there is no register conflict, and subsequent operations proceed in the same way as in that case.

A case in which the calculation result in the ALU 330 does not match the previous calculation result will be described next. In the above explanation, FIG. 7 has been used as a timing chart, but in the following explanation, FIG. 8 will be used. in this case.

rO'' is applied to the signal line 586. This rOJ is input to selectors 300 and 308. At this time, the selector 300 outputs the data on the signal line 504 to the signal line 506, and the selector 308 outputs the data on the signal line 504 to the signal line 506.
Output to 18. As a result, at time T5, the IC5V register 1 is stored in the prefetch instruction address register 100.
The upper two instruction addresses of the second instruction stored in 16
A 0 bit is stored. This value is the same as the prefetch addresses for the first to fourth instructions. As a result, lookahead is executed, and at time T6, the first to fourth instructions are transferred to the instruction buffers 7104, 106, 108 . Stored in ilO. Since the instruction address of the second instruction is applied to the signal line 518, the second instruction on the instruction register 106 is stored in the instruction register 112 at time T7. At time 5, the first instruction causing a register conflict with the second instruction has already written the operation result to the register indicated by the R1 field. Therefore, at time T7, the operation proceeds in the same manner as in the case where there is no register conflict between the first and second instructions.

Additionally, a "0" on signal line 586 is applied to the content addressable memory. As a result, the IC storage section 346 of the associative memory device.
IR storage section 34B, X2L/Jister value storage section 350. B
2 register value storage unit 352° prefetch instruction address storage unit 354. The data storage unit 356 and the address storage unit 345 respectively store the instruction address of the first instruction on the signal line 580, the first instruction word on the signal line 564, the x2 register value of the first instruction on the signal line 578, and the 82 register value of the first instruction, the prefetch instruction address when prefetching the first instruction on the signal line 574, the operation result of the first instruction on the signal line 556, the operand address of the first instruction on the signal line 708, A word whose flag storage unit is "1" is registered at time T5.

This concludes the explanation of the case where the calculation result in the ALU 330 does not match the previous calculation result.

Furthermore, this concludes the description of the case where the associative memory device contains the calculation results from the previous execution.

A store instruction is executed and the store
If the address is equal to the operand address of an instruction stored in associative memory, the result of the operation of this instruction stored in associative memory will be different from the result of the operation when that instruction is subsequently executed. . When a store instruction is executed, the operation result in the associative memory can be rewritten with store data.The process will be described below.

As already mentioned in the description of content addressable memory 320.

When a store instruction is executed, the signal line 712
``1'' is transferred to the content addressable memory device via . At the same time, the operand address (i.e., store address) of the store instruction is transferred via signal line 708, and the contents of the R1 register (i.e., store data) of the store instruction are transferred via signal line 560. is transferred.

At this time, the associative memory device searches for all words whose address storage unit ADDR is equal to the store address, rewrites the data storage unit DATAP of the equal word with the store data, and rewrites the flag storage unit of that word to "1". Ru.

This concludes the explanation of the processing when a store instruction is executed.

Next, a case where the content addressable memory device has the second operand (memory operand) of the preceding instruction will be described.

FIG. 7 is used as a timing chart.

In this case, when the store instruction is executed as described above, the data in the associative memory (the previous operation result of the first instruction or the
Stores the memory data (second operand) of the instruction.
Because it is rewritten with data.

The second operand in the associative memory is always correct, and in this case, for this second operand, the first
Since the operation is performed using the first operand when executing the instruction,
The result of the operation is different from the result of the previous operation stored in the associative memory and is correct. Therefore, in this case, as described above, the result of the previous operation is compared with the result of the operation in the ALU and the result of the operation is correct. There is no need to redo the two instructions.

Most of the instruction prefetching from the first instruction to the fourth instruction and the processing of the first instruction are the same as those in the case where there is no register conflict as described above. That is, in the timing chart of FIG. 7, IFA regarding the first to fourth instructions, IBO to IFASV, I
R/IC, OA/IRI/ICI/GRXI/GRBI
/IFAI.

OD/IR2/IC2/GRX2/GRB2/IFA2
．． The timing of GR is the same as in FIG. The other parts will be explained below.

First, from time To, the prefetch instruction address register 100
The prefetch instruction address stored in the signal line 500
The prefetch instruction address storage unit IF of the associative memory device via
It is applied to AP354. Also, at time T2, the instruction word of the first instruction, the instruction address X2 register value, B2
The register values are respectively connected to signal lines 522, 530, 540,
542 respectively to the IR storage unit 34 of the associative memory device.
8°IC storage section 346. X2 register value storage section 350° is applied to B2 register value storage section 352.

The associative memory device includes the signal lines 530, 522, 540,
Search using 542,500 data.

Now, we are considering the case where the associative memory device has the second operand (memory operand) of the preceding instruction, so the time T
3, the DATAL register 158 stores the second operand of the first instruction, that is, the preceding instruction, and FLGL
“0” is stored in the register 157, and “1” is stored in the IIITL register 156. Furthermore, this "1"
is applied to signal line 546.

At time T3, the IRI register 124 stores the instruction word of the first instruction, Add instruction, and the instruction register 112 stores the instruction word of the second instruction, 5ubstract instruction. Therefore, "5" in the R1 field of the first instruction is applied to the signal line 582, and "5J" in the x2 field of the second instruction is applied to the signal line 542. Since it is assumed that there is no register confrifter, the signal lines 558 and 526
A value different from "5" is applied to . Therefore, the output of the minus number comparison circuit 160 becomes "1", and the outputs of the other coincidence comparison circuits 162, 164, and 166 become "0". Therefore, the output signal line 593 of the OR circuit 168 and the OR circuit 1
82 output signal line and the output signal 81 of the AND circuit 172
72 becomes “1”・Also, the output signal line 59 of the OR circuit
1 and the output signal line 590 of the AND circuit 174. AND times
The output signal line of l180 becomes "0".

The second operand of the first instruction is input to the ALU 360 via the signal l1538, and the second operand of the first instruction is input to the ALU 360 via the signal line 606.
The contents of the R1 register of the instruction, ie, the first operand, are input, and the opcode of the first instruction is input via the signal line 604. The ALU 360 thereby performs the calculation of the first instruction and outputs the calculation result onto the signal line 600.

Since the signal line 592 is "1" and the signal line 714 is rOJ, the selector 316 selects the signal line 6 as shown in FIG.
The operation result of the first instruction on the signal line 540 is applied to the address adder 324, and the selector 318 applies the B2 register value of the second instruction on the signal line 536 to the signal ff154.
2 to the address adder 324. signal line 5
From 28, the displacement of the second instruction is applied to the address adder.

As a result, the second instruction operand address is stored in the operand address register 120 at time T4.

Also, IRI register 124. MCI register 130,
GRXL register 132. GRBI register 134. I
The same data as the operation when there is no register conflict is stored in the FAI register 136 at time T4.

The subsequent operation of the second instruction proceeds in the same way as in the case where there is no register conflict.

This concludes the explanation of the case where the second operand of the preceding instruction is in the associative memory device.

Next, effects specific to this embodiment will be described.

When the present invention is not used, if a subsequent instruction that has a register conflict with a preceding instruction is executed, the operation will be the same as when there is no information about the previous execution in the associative memory 'A' in the operation explanation above, and there will be two periods of idle time. will occur.

With this invention, there will be no free time at all,
Improves instruction processing performance when a register conflict occurs.

In the above-described embodiment, as the operation result of the preceding instruction, the previous operation result of the preceding instruction stored in the associative memory or the second operand (memory operand) of the preceding instruction stored in the associative memory is used. The first operand of the preceding instruction was used to perform an operation on the previous instruction, and the result was used. However, the present invention.

The previous operation result of the preceding instruction is not stored in the associative memory.
The present invention can also be applied to a case where the second operand of the preceding instruction is always stored and the result of performing an operation on the second operand using the first operand of the preceding instruction is always used as the operation result of the preceding instruction.

Examples in this case are shown in FIGS. 11A, 1] and B.

Associative memory in this diagram shows that when there is no information in associative memory, there is a third
The second operand of the preceding instruction is stored via the signal line 554 instead of the signal line 556 in FIGS. A and 3B, and the flag storage section is set to "0". In this way, the second operand of the preceding instruction is always stored in the associative memory. Therefore, when the second operand is stored in associative memory,
As in the above embodiment, subsequent instructions can be executed without any idle time.

Also, Figures 3A and 3B and Figures 11A and 11B
In the two illustrated embodiments, when a store instruction is executed, store data is used to rewrite information in the content addressable memory.

However, the present invention can also be applied to the case where, when a store instruction is executed, a word whose store address and operand address match is invalidated.

In this case, the associative memory 320 in FIG.
The configuration may be such that when "1" is applied to 2, the word whose address storage unit is the same as the store address on the signal line 708 is deleted from the associative memory. In this case as well, when information is stored in the associative memory, subsequent instructions can be executed without idle time as in the above embodiment.

Further, as the associative keys, all of the above-mentioned keys can be used, or any combination can be used. In this case, it is also possible to use some bit positions of the key components.

〔Effect of the invention〕

If the present invention is not used, it takes address calculation time, operand read time, and calculation time for the preceding instruction after the preceding instruction that causes a register conflict is started until the subsequent instruction is started.

However, by using the present invention, it only takes time from inputting the associative key to the prediction device until outputting the predicted value.The latter time varies depending on what is used for the associative key, but Even in the worst case where an address is used as an associative key, the time is much shorter than when the present invention is not used.

[Brief explanation of drawings]

Figure 1A is an instruction format diagram, Figure 1B is an example of a load instruction, Figure 2 is an example of two instructions that cause a register conflict,
3A and 3B are general configuration diagrams of the embodiment, FIG. 4 is a configuration diagram of an associative memory device, FIGS. 5 to 8 are timing chart diagrams, and FIG. 9 is a configuration diagram of a register conflict detection device.
FIG. 10 is an operation diagram of the selector, and FIGS. 11A and 11B are overall configuration diagrams of other embodiments. 100...Prefetch instruction address register, 304...
・Instruction storage device, 104, 106, 108, 110...
・Instruction buffer, 112...Instruction register, 114・
...Instruction counter, 324...Address adder. 120...operand address register, 326...
... Operand storage device, 126 ... Operand data register, 330 ... ALU, 118 ... Register file, 320 ... Associative memory, 322 ... Register conflict detection device.

Claims (1)

[Claims] 1. When a subsequent instruction is executed using an operation result written to a register by a preceding instruction, the operation of the subsequent instruction is performed until the operation result is determined. In a data processing device that stops processing using a result, the instruction address of the preceding instruction, the instruction address of the instruction before the preceding instruction, the read-ahead address when reading ahead of the preceding instruction, and the instruction before the preceding instruction. When prefetching, all of the prefetch addresses or a combination of each arbitrary bit position data and the memory operand of the preceding instruction.
means for storing a memory operand address and an operation result of the preceding instruction in association with an associative key consisting of address determination information; associative writing means for searching whether or not the memory operand address matching the address exists in the storage means and, at some times, rewriting the corresponding operation result with store data of the store instruction; means for searching the storage means based on the associative key at that time when executed, and outputting the operation result or the memory operand corresponding to the associative key when the associative key is stored; When the operation result is output, the operation result from the output means is used to start the processing of the stopped subsequent instruction, and the operation result from the output means is the operation result obtained by the operation of the preceding instruction. If it is equal to , continue processing the started subsequent instruction; if not equal,
means for invalidating the processing of the subsequent instruction and re-executing the processing of the subsequent instruction using the operation result obtained from the operation of the preceding instruction; and when the memory operand is output from the output means, the memory operand is A data processing device comprising means for performing an operation specified by the preceding instruction on an operand and using the result of the operation to start processing of the stopped subsequent instruction. 2. When a subsequent instruction is executed using the operation result written to the register by the preceding instruction, the processing of the subsequent instruction that uses the operation result is stopped until the operation result is finalized. In a data processing device, an instruction address of the preceding instruction, an instruction address of an instruction before the preceding instruction, a look-ahead address when reading ahead the preceding instruction, a look-ahead address when reading ahead the instruction before the preceding instruction, or a combination of arbitrary bit position data of each and the memory operand of the preceding instruction.
means for storing a memory operand address and a memory operand of the preceding instruction in association with an associative key consisting of address determination information; an associative write means for searching whether the memory operand address that matches the address exists in the storage means and, at some times, rewriting the corresponding memory operand with store data of the store instruction; searching the storage means based on the associative key at the time the instruction is executed;
means for outputting the memory operand corresponding to the associative key when it is stored; and when the memory operand is output from the output means, performing the operation specified by the preceding instruction on the memory operand. 1. A data processing device comprising: means for performing processing on a subsequent instruction that has been stopped, and using the result of the calculation to start processing of the subsequent instruction that has been stopped. 3. When a subsequent instruction is executed using the operation result written to the register by the preceding instruction, the processing of the subsequent instruction that uses the operation result is stopped until the operation result is finalized. In a data processing device, all of the instruction address of the preceding instruction, the instruction address before the preceding instruction, the pre-reading address when reading ahead the preceding instruction, and the read-ahead address when reading ahead the instruction before the preceding instruction. or means for storing the memory operand address and operation result of the preceding instruction in association with an associative key consisting of each arbitrary bit position data combination and memory operand address determination information of the preceding instruction; , When a store instruction is executed by the data processing device, the memory operand address that matches the store address of the store instruction is searched for in the storage means, and in some cases, the corresponding associative key and an associative means for deleting a memory operand address and an operation result; and when the preceding instruction is executed, the storage means is searched based on the associative key at that time, and when the associative key is stored, it is searched for. means for outputting the operation result or the memory operand; and when the operation result is output from the output means, the operation result from the output means is used to start processing of the stopped subsequent instruction. , if the operation result from the output means is equal to the operation result obtained by the operation of the preceding instruction, the started processing of the subsequent instruction is continued; if they are not equal,
means for invalidating the processing of the subsequent instruction and re-executing the processing of the subsequent instruction using the operation result obtained from the operation of the preceding instruction; and when the memory operand is output from the output means, the memory operand is A data processing device comprising means for performing an operation specified by the preceding instruction on an operand and using the result of the operation to start processing of the stopped subsequent instruction. 4. When a subsequent instruction is executed using the operation result written to the register by the preceding instruction, the processing of the subsequent instruction that uses the operation result is stopped until the operation result is finalized. In a data processing device, an instruction address of the preceding instruction, an instruction address of an instruction before the preceding instruction, a look-ahead address when reading ahead the preceding instruction, a look-ahead address when reading ahead the instruction before the preceding instruction, or a combination of arbitrary bit position data of each and the memory operand of the preceding instruction.
means for storing a memory operand address and a memory operand of the preceding instruction in association with an associative key consisting of address determination information; an associative means for searching whether the memory operand address that matches the address exists in the storage means and, in some cases, deleting the corresponding associative key, memory operand address, and memory operand; means for searching the storage means based on the associative key at that time when an instruction is executed, and outputting the memory operand corresponding to the associative key when the associative key is stored; When the operand is output, the method is characterized by having means for performing an operation specified by the preceding instruction on the memory operand, and using the result of the operation to start processing of the stopped subsequent instruction. Data processing equipment.